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S5N8947 DATA SHEET
GENERAL DESCRIPTION
Samsung's S5N8947 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution. The S5N8947 is designed as 2-channel 10/100Mbps Ethernet controller for use in managed communication hubs and routers. The S5N8947 also provides ATM Layer SAR (Segmentation and Reassembly) function with UTOPIA interface and the full-rate USB (Universal Serial Bus) function. The S5N8947 is built around an outstanding CPU core: the 16/32-bit ARM7TDMI RISC processor designed by Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general purpose, microprocessor macrocell that was developed for use in application-specific and custom-specific integrated circuits. Its simple, elegant, and fully static design is particularly suitable for cost-sensitive and power-sensitive applications. Important peripheral functions including an UART channel, 2-channel GDMA, three 32-bit timers, watchdog timer, 2 I C bus controller, SPI, and programmable I/O ports are supported. Built-in logic including an interrupt controller, DRAM controller, and a controller for ROM/SRAM and flash memory are also supported. The S5N8947's System Manager provides an internal 32-bit system bus arbiter and an external memory controller including control logic for a PCMCIA socket interface. To reduce total system cost, the S5N8947 offers a unified cache, 2-channel 10/100Mbps Ethernet controller, SAR and USB. Most of the on-chip function blocks have been designed using an HDL synthesizer and the S5N8947 has been fully verified in Samsung's state-of-the-art ASIC test environment. Table 1-1. S5N8946 vs. S5N8947 Item Architecture S5N8946 Only one mode: 10Base-T + SAR + USB 2 timer Function UTOPIA level 1 support Seven wire support (10 Mbps Ethernet Support) USB support byte access. SAR support hardwired big endian. Performance Operation Condition Package 50MHz operation 4K unified cache 3.3V 240 QFP S5N8947 Two modes are supported: Mode 1. MII + SAR + USB + PCMCIA Mode 2. 2xMII + SAR + USB 3 timer 1 watchdog timer SPI interface support PCMCIA support UTOPIA level 1/2 support MII/Seven wire support (10/100 Mbps Ethernet Support) USB support word access and DMA operation. SAR support hardwired Big/Little endian. 72MHz operation 8K unified cache 1.8V 208 LQFP
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FEATURES
-- 8-Kbyte unified cache -- SAR (Segmentation and Reassembly) -- UTOPIA (the Universal Test & Operations PHY Interface for ATM) Level 1/2 Interface -- 2-channel 10/100Mbps Ethernet -- Full-rate USB controller -- 2-CH GDMA (General Purpose Direct Memory Access) -- UART (Universal Asynchronous Receiver and Transmtter) -- 3 programmable 32bits Timers -- Watchdog Timer -- 18 Programmable I/O ports -- Interrupt controller -- I C controller -- SPI (Serial Peripheral Interface) -- Built-in PLLs for System/USB -- PCMCIA `memory and I/O' master modes -- Cost effective JTAG-based debug solution -- Boundary scan -- 3.3V I/Os and 1.8V core supply voltage -- Operating Frequency Up to 72MHz -- 208 LQFP Package
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S5N8947 DATA SHEET
FUNCTIONAL BLOCK DESCRIPTIONS
BLOCK DIAGRAM Mode 1 (1 SAR + 1 MII + 1 PCMCIA + 1 USB)
ARM7TDMI 32bit RISC CPU
ICE Breaker 32-bit System Bus Memory Controller with Refresh Control
3-Bank ROM SRAM FLASH 4-Bank DRAM 4-Bank External I/O Device External Bus Master PCMCIA I/F
CPU Interface
Unified CACHE 4-word Write Buffer Bus Router
Connection Memory 18 General I/O Ports Interrupt Controller 32bit Timer 0, 1, 2 Ethernet MAC Watchdog Timer GDMA 0, 1 SPI Controller USB Interface Osc PLL* (USB)
SAR/UTOPIA
UART IIC Controller
PLL* (System) TAP Controller for JTAG
Figure 1-1. Top Block Diagram: Mode 1
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Mode 2 (1 SAR + 2 MII + 1 USB)
ARM7TDMI 32bit RISC CPU
ICE Breaker 32-bit System Bus
3-Bank ROM SRAM FLASH Memory Controller with Refresh Control 4-Bank DRAM 2-Bank External I/O Device External Bus Master
CPU Interface
Unified CACHE 4-word Write Buffer Bus Router
System Bus Arbiter Connection Memory
5 General I/O Ports Interrupt Controller 32bit Timer 0, 1, 2 Ethernet MAC Ethernet MAC Watchdog Timer GDMA 0, 1 SPI Controller ( 3 GPIO Pins ) UART (Internal Clock Only) IIC Controller USB Interface Osc
SAR/UTOPIA
PLL* (USB)
PLL* (System) TAP Controller for JTAG
Figure 1-2. Top Block Diagram: Mode 2
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S5N8947 DATA SHEET
ARCHITECTURE -- Integrated system for embedded Ethernet / USB / SAR -- Fully 16/32-bit RISC architecture -- Efficient and powerful ARM7TDMI core -- Little/Big-Endian mode is fully supported. (The internal register supports word access only.) -- Cost-effective JTAG-based debug solution -- Supports Boundary Scan
SYSTEM MANAGER -- 8/16/32-bit external bus support for ROM/SRAM, flash memory, DRAM and external I/O -- One external bus master with bus request/acknowledge pins -- Supports EDO/normal or SDRAM -- Programmable access cycle -- Four-word depth write buffer -- Cost-effective memory-to-peripheral DMA interface -- Supports PCMCIA `memory and I/O' master mode
UNIFIED INSTRUCTION/DATA CACHE -- Two-way set-associative unified cache (8Kbytes) -- Supports LRU (least recently used) Protocol
SAR/UTOPIA INTERFACE -- Directly supports ATM Adaptation Layer Five (AAL5) Segmentation And Reassembly -- Segments and reassembles data up to 70Mbps -- A glueless UTOPIA level 1/2 interface is supprted (for receiving and transmitting ATM cells with SAR, it is a standard ATM interface between ATM link and physical layer).
ETHERNET -- 2-Channel 10/100Mbps Ethernet Controller -- 4 DMA engines with burst mode -- Full compliance with IEEE standard 802.3 -- Supports MII interface (7-wire 10-Mbps interface is also supported).
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USB CONTROLLER Supports 12Mbps full rate function for universal serial bus DMA CONTROLLER -- 2-channel general purpose DMA (for memory-to-memory, memory-to-SPI, SPI-to-memory, UART-tomemory, memory-to-UART data transfers without CPU intervention) -- Initiated by a software or a external DMA request -- Increments or decrements source or destination address in 8-bit, 16-bit, or 32-bit data transfers
UART -- UART block with DMA-based or interrupt-based operation -- Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit and receive -- Programmable baud rates -- Infra-red (IR) TX/RX support (IrDA)
TIMERS -- Three programmable 32-bit timers -- Interval mode or toggle mode operation -- Supports a watchdog timer
PROGRAMMABLE I/O -- 18 programmable I/O ports -- Pins individually configurable to input, output, or I/O mode for dedicated signals
INTERRUPT CONTROLLER -- 23 interrupt sources, including 7 external interrupt sources -- Normal or fast interrupt mode (IRQ, FIQ) -- Prioritized interrupt handling
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S5N8947 DATA SHEET
I2C SERIAL INTERFACE -- Single master mode operation only
SPI -- Full duplex operation -- Work with data characters from 4 to 32 bits long -- Supports GDMA mode for SPI transmission and reception -- Single master SPI modes only supported -- Programmable baud rate generator -- Programmable clock phase and polarity
PLLS -- The external clock can be multiplied by on-chip PLLs to provide high frequency System/USB clock -- The input frequency is fixed to 12MHz -- The output frequency is 6 times the input clock for System -- The output frequency is 4 times the input clock for USB
NOTE Refer to the Board guides for clock frequency which can be usable. CM47_M66_MANUAL_V1.0.doc CM47_M72_MANUAL10.doc
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PIN DESCRIPTIONS
PIN CONFIGURATION
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
B0SIZE[0] B0SIZE[1] unconnection nRESET OSC_XIN unconnection GND36 XCLK_I GND1 FILTER_S FILTER_U VDD3/4 GND3/4 ExtMREQ ExtMACK BIGEND MCLKO GND5 unconnection VDD5 nTRST TMS TCK TDI TDO nDTACK nOE nECS[0] nECS[1] nECS[2] nECS[3] nRCS[0] nRCS[1] nRCS[2] VDD7/8 GND7/8 nRCS[3] nRAS[0] nRAS[1] nRAS[2] nRAS[3] nCAS[0] nCAS[1] nCAS[2] nCAS[3] nDWE nWBE[0] VDD9 GND9 nWBE[1] nWBE[2] nWBE[3]
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
UTO_RXD[1] UTO_RXD[2] UTO_RXD[3] UTO_RXD[4] GND27 VDD27 UTO_RXD[5] UTO_RXD[6] UTO_RXD[7] UTO_RXSOC UTO_RXENB UTO_RXCLAV UTO_CLK SCL SDA UCLK UARXD UATXD nUADTR VDD29/35 GND29/35 nUADSR MDC MDIO COL RXD[0] RXD[1] RXD[2] RXD[3] RX_DV RX_CLK RX_ERR TX_CLK TXD[0] VDD31/32 GND31/32 TXD[1] TXD[2] TXD[3] TX_EN TX_ERR CRS USB_DP USB_DN SPIMISO SPIMOSI SPICLK VDD33 GND33 TMODE FMODE CLKSEL
UTO_RXD[0] UTO_RXADR[1] UTO_RXADR[0] GND25 VDD25 UTO_TXCLAV UTO_TXENB UTO_TXSOC UTO_TXD[7] UTO_TXD[6] UTO_TXD[5] UTO_TXD[4] UTO_TXD[3] UTO_TXD[2] UTO_TXD[1] UTO_TXD[0] GND23/24 VDD23/24 UTO_TXADR[1] UTO_TXADR[0] P[17] P[16] P[15] P[14] P[13] P[12] P[11] P[10] P[9] P[8] P[7] GND21 VDD21 P[6] P[5] P[4] P[3] P[2] P[1] P[0] DATA[31] DATA[30] DATA[29] DATA[28] DATA[27] DATA[26] VDD19 GND19 DATA[25] DATA[24] DATA[23] DATA[22]
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 DATA[21] DATA[20] DATA[19] GND17 VDD17 DATA[18] DATA[17] DATA[16] DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8] GND15/16 VDD15/16 DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] ADDR[21] ADDR[20] ADDR[19] ADDR[18] ADDR[17] GND13/34 VDD13/34 ADDR[16] ADDR[15] ADDR[14] ADDR[13] ADDR[12] ADDR[11] ADDR[10] ADDR[9] ADDR[8] ADDR[7] ADDR[6] ADDR[5] ADDR[4] VDD11 GND11 ADDR[3] ADDR[2] ADDR[1] ADDR[0]
S5N8947 208-LQFP-2828 (Top View)
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
Figure 1-3. S5N8947 Pin Configuration NOTE Under-bar in the Figure 1-3 means the muxing pins.
S5N8947 DATA SHEET
LOGIC SYMBOL DIAGRAM Mode 1 (1 SAR + 1 MII + 1 PCMCIA + 1 USB)
S5N8947
( FMODE = 0 ) nRESET OSC_XIN XCLK_I FILTER_S FILTER_U MCLKO TMODE FMODE CLKSEL BIGEND nTRST TMS TCK TDI TDO ADDR[21:0] DATA[31:0] B0SIZE[1:0] nDTACK nOE nECS[3:0] nRCS[3:0] nRAS[3:0] nCAS[3:0] nDWE nWBE[3:0] ExtMREQ ExtMACK UCLK UARXD UATXD nUADTR nUADSR SPIMISO SPIMOSI SPICLK P[17:0] External I/F & GPIO Signals SCL SDA System UTOPIA L 1/2 UTO_TXADR[1:0] UTO_TXD[7:0] UTO_TXSOC UTO_TXENB UTO_TXCLAV UTO_RXADR[1:0] UTO_RXD[7:0] UTO_RXSOC UTO_RXENB UTO_RXCLAV UTO_CLK MDC MDIO COL RXD[3:0] RX_DV RX_CLK RX_ERR TX_CLK TXD[3:0] TX_EN TX_ERR CRS USB_DP USB_DN
Mode
JTAG MII
Memory & External Interface
USB
UART
SPI GPIO PCMCIA IICC
Figure 1-4. S5N8947 Logic Symbol Diagram (Mode 1)
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Mode 2 (1 SAR + 2 MII + 1 USB)
S5N8947
( FMODE = 1 ) nRESET OSC_XIN XCLK_I FILTER_S FILTER_U MCLKO TMODE FMODE CLKSEL BIGEND nTRST TMS TCK TDI TDO ADDR[21:0] DATA[31:0] B0SIZE[1:0] nDTACK nOE nECS[2:0] nRCS[3:0] nRAS[3:0] nCAS[3:0] nDWE nWBE[3:0] ExtMREQ ExtMACK UARXD UATXD nUADTR nUADSR SPIMISO SPIMOSI SPICLK P[4:0] SCL SDA System UTOPIA L 1/2 UTO_TXADR[1:0] UTO_TXD[7:0] UTO_TXSOC UTO_TXENB UTO_TXCLAV UTO_RXADR[1:0] UTO_RXD[7:0] UTO_RXSOC UTO_RXENB UTO_RXCLAV UTO_CLK MDC MDIO COL RXD[3:0] RX_DV RX_CLK RX_ERR TX_CLK TXD[3:0] TX_EN TX_ERR CRS MDC MDIO COL RXD[3:0] RX_DV RX_CLK RX_ERR TX_CLK TXD[3:0] TX_EN TX_ERR CRS USB_DP USB_DN
Mode
JTAG MII
Memory & External Interface
MII
UART
SPI
USB
GPIO IICC
Figure 1-5. S5N8947 Logic Symbol Diagram (Mode 2)
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S5N8947 DATA SHEET
Table 1-2. Pin Descriptions with the Pin number and Pad type Pin No 1 2 *3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 *19 20 21 22 23 24 25 26 27 28 29 *30 *31 32 33 34 Pin Name B0SIZE[0] B0SIZE[1] unconnection nRESET OSC_XIN unconnection GND36 XCLK_I GND1 FILTER_S FILTER_U VDD3/4 GND3/4 ExtMREQ ExtMACK BIGEND MCLKO GND5 Unconnection VDD5 nTRST TMS TCK TDI TDO NDTACK NOE NECS[0] NECS[1] NECS[2] NECS[3] nRCS[0] nRCS[1] nRCS[2] I/O Type I I I I I O P I P O O P P I O I O P B P I I I I O I O O O O O O O O Pad Type Phic Phic Phic Phtis Phsoscm2 Phsoscm2 Vss3o phic Vbb1_abb Poar50_abb Poar50_abb Vdd1t_abb Vss1t_abb Phic Phob1 Phicd Phob8 Vss3p Phbcut4 Vdd3p Phicu Phicu phic Phicu Phtot2 Phicu Phot4 Phot4 Phot4 Phot4 Phot4 Phot4 Phot4 Phot4 Muxing with sTXD[3] Muxing with sMDC Muxing with sMDIO 3.3V 1.8V OSC input Muxing with sRX_CLK Descriptions
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Table 1-2. Pin Descriptions with the Pin number and Pad type (Continued) Pin No 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53-56 57 58 59-71 72 73 74-78 79-86 87 88 89-99 100 101 102-108 109 110 111-116 Pin Name VDD7/8 GND7/8 nRCS[3] nRAS[0] nRAS[1] nRAS[2] nRAS[3] nCAS[0] nCAS[1] nCAS[2] nCAS[3] nDWE nWBE[0] VDD9 GND9 nWBE[1] nWBE[2] nWBE[3] ADDR[0:3] GND11 VDD11 ADDR[4:16] VDD13/34 GND13/34 ADDR[17:21] DATA[0:7] VDD15/16 GND15/16 DATA[8:18] VDD17 GND17 DATA[19-25] GND19 VDD19 DATA[26-31] I/O Type P P O O O O O O O O O O O P P O O O O P P O P P O B P P B P P B P P B Pad Type Vdd3o Vss3o Phot4 Phot4 Phot4 Phot4 Phot4 Phot4 Phot4 Phot4 Phot4 Phot4 Phot8 Vdd1ih Vss3i Phot8 Phot8 Phot8 Phot4 Vss3i Vdd1ih Phot8 Vdd3o Vss3o Phot8 Phbcut8 Vdd3o Vss3o Phbcut8 Vdd1ih Vss3i Phbcut8 Vss3I Vdd1ih Phbcut8 1.8V 1.8V 3.3V 3.3V 1.8V nWBE[1]/IORD(PCMCIA only) nWBE[2]/IOWR(PCMCIA only) 1.8V Not PCMCIA select 3.3V Descriptions
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S5N8947 DATA SHEET
Table 1-2. Pin Descriptions with the Pin number and Pad type (Continued) Pin No 117-120 *121 *122 *123 124 125 *126 127-129 *130 *131 *132 *133 *134 135 *136 137-138 139 140 141-145 *146 *147 *148 149 150 151 152 153 154-155 *156 *157 *158 *159 *160 161 P[4] P[5] P[6] VDD21 GND21 P[7] P[8-10] P[11] P[12] P[13] P[14] P[15] P[16] P[17] UTO_TXADR[0:1] VDD23/24 GND23/24 UTO_TXD[0:4] UTO_TXD[5] UTO_TXD[6] UTO_TXD[7] UTO_TXSOC UTO_TXENB UTO_TXCLAV VDD25 GND25 UTOP_RXADR[0:1] UTO_RXD[0] UTO_RXD[1] UTO_RXD[2] UTO_RXD[3] UTO_RXD[4] GND27 Pin Name P[0:3] I/O Type B B B B P P B B B B B B B B B O P P O O O O O O I P P O I I I I I P Pad Type Phbcut4 Phbcut4 Phbcut4 Phbcut4 Vdd3p Vss3p Phbcut4 Phbcut4 Phbcut4 Phbcut4 Phbcut4 Phbcut4 Phbcut4 Phbcut4 Phbcut4 Phob4 Vdd3o Vss3o Phob4 Phob4 Phob4 Phob4 Phob4 Phob4 Phtis Vdd1ih Vss3i Phob4 phtis phtis phtis phtis phtis Vss3i Muxing with bist_on Muxing with bist_mode Muxing with bist_memsel[0] Muxing with bist_memsel[1] Muxing with bist_memsel[2] 1.8V Muxing with bist_errob Muxing with bist_diag Muxing with bist_done 3.3V Muxing with sRX_ERR Muxing with sCRS Muxing with sRXD[0] Muxing with sRXD[1] Muxing with sRXD[2] Muxing with sRXD[3] Muxing with sRX_DV Muxing with sTXD[0] Muxing with sTXD[1] Muxing with sTXD[2] 3.3V Descriptions
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Table 1-2. Pin Descriptions with the Pin number and Pad type (Continued) Pin No 162 *163 164-165 166 167 168 169 170 171 *172 173 174 175 176 177 178 179 180 181 *182 *183 *184 *185 186 187 188 189 190 191 192 193-195 196 197 198 199 Pin Name VDD27 UTO_RXD[5] UTO_RXD[6:7] UTO_RXSOC UTO_RXENB UTO_RXCLAV UTO_CLK SCL SDA UCLK UARXD UATXD nUADTR VDD29/35 GND29/35 nUADSR MDC MDIO COL RXD[0] RXD[1] RXD[2] RXD[3] RX_DV RX_CLK RX_ERR TX_CLK TXD[0] VDD31/32 GND31/32 TXD[1:3] TX_EN TX_ERR CRS USB_DP I/O Type P I I I O I O B B I I O I P P O O B I I I I I I I I I O P P O O O I B Pad Type Vdd1ih phtis phtis Phtis Phob4 Phtis Phob4 Phbcud4 Phbcud4 phic Phic Phob4 Phic Vdd3o Vss3o Phob4 Phob4 Phbcut4 Phic Phic Phic Phic Phic Phic Phic Phic Phic Phob4 Vdd3o Vss3o Phob4 Phob4 Phob4 Phic Pbusbfs 7-wire pin 7-wire pin 7-wire pin 7-wire pin 3.3V 7-wire pin 7-wire pin Muxing with test_mode[0], 7-wire pin Muxing with test_mode[1] Muxing with test_mode[2] Muxing with test_mode[3] 3.3V Muxing with sTX_CLK 1.8V Muxing with bist_memsel[3] Descriptions
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S5N8947 DATA SHEET
Table 1-2. Pin Descriptions with the Pin number and Pad type (Continued) Pin No 200 *201 *202 *203 204 205 206 207 208 Pin Name USB_DN SPIMISO SPIMOSI SPICLK VDD33 GND33 TMODE FMODE CLKSEL I/O Type B I O O P P I I I Pad Type Pbusbfs Phic Phob4 Phob4 Vdd1ih Vss3i Phic Phic phic SPI input data, Muxing with sCOL SPI output data, Muxing with sTX_EN SPI clock, Muxing with sTX_ERR 1.8V Descriptions
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PAD DESCRIPTIONS Input PADs Pad Types PHIC / PHICS / PHICU PHIS / PHISD / PHISU PHTIS / PHTISD / PHTISU Descriptions 3.3V interface LVCMOS level input buffer 3.3V interface LVCMOS schmitt trigger level input buffer 5V tolerant for 3.3V interface CMOS schmit trigger level input buffer
Output PADs Pad Types PHOB (1/4/8) PHOT (1/4/8) Descriptions 3.3V LVCMOS normal output buffers 3.3V LVCMOS tri-state output buffers
Bi-Direction PADs Pad Types PHBCUT4 (PHBaTyz) PHBCUD4 (PHBaUDyz) 3.3V tri-state bi-direction buffers 3.3V open-drain bi-directional buffers with pull-up Descriptions
Power Pads Pad Characteristics 1.8V Interface Digital I/O 3.3V Interface Digital I/O 1.8V Interface Digital I/O 3.3V Interface Digital I/O 1.8V Interface Analog I/O 1.8V Interface Analog I/O Pad Types vdd1i Vdd3p Vdd3o Vss1i Vss3p Vss3o Vdd1t_abb Vss1t_abb Vss1_abb 1.8V Supply Voltage 1.8V 3.3V 3.3V 1.8V internal 3.3V pre-driver 3.3V output-driver Internal GND for 1.8V interface I/O Pre-driver GND for 3.3V interface I/O Output-driver GND for 3.3V interface I/O 1.8V total Total GND for 1.8V interface I/O Bulk-bias GND for 1.8V interface I/O Descriptions
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S5N8947 DATA SHEET
OPERATION DESCRIPTION
CPU CORE OVERVIEW The S5N8947 CPU core is the ARM7TDMI processor, a general purpose, 32-bit microprocessor developed by Advanced RISC Machines, Ltd. (ARM). The core's architecture is based on Reduced Instruction Set Computer (RISC) principles. The RISC architecture makes the instruction set and its related decoding mechanisms simpler and more efficient than those with microprogrammed Complex Instruction Set Computer (CISC) systems. The resulting benefit is high instruction throughput and impressive real-time interrupt response. Pipelining is also employed so that all components of the processing and memory systems can operate continuously. The ARM7TDMI has a 32-bit address bus. An important feature of the ARM7TDMI processor, and one which differentiates it from the ARM7 processor, is a unique architectural strategy called THUMB. The THUMB strategy is an extension of the basic ARM architecture and consists of 36 instruction formats. These formats are based on the standard 32-bit ARM instruction set, but have been re-coded using 16-bit wide opcodes.
Address Register Address Incrementer Register Bank Instruction Decoder and Logic Controll
Multiplier Barrel Shifter 32-BIT ALU Write Data Register
Instruction Pipeline and Read Data Register
Figure 1-6. ARM7TDMI Core Block Diagram Because THUMB instructions are one-half the bit width of normal ARM instructions, they produce very highdensity code. When a THUMB instruction is executed, its 16-bit opcode is decoded by the processor into its equivalent instruction in the standard ARM instruction set. The ARM core then processes the 16-bit instruction as it would a normal 32-bit instruction. In other words, the THUMB architecture gives 16-bit systems a way to access the 32-bit performance of the ARM core without incurring the full overhead of 32-bit processing. Because the ARM7TDMI core can execute both standard 32-bit ARM instructions and 16-bit THUMB instructions, it lets you mix routines of THUMB instructions and ARM code in the same address space. In this way, you can adjust code size and performance, routine by routine, to find the best programming solution for a specific application.
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INSTRUCTION SET The S5N8947 instruction set is divided into two subsets: a standard 32-bit ARM instruction set and a 16-bit THUMB instruction set. The 32-bit ARM instruction set is comprised of thirteen basic instruction types which can be divided into four broad classes: -- Four types of branch instructions which control program execution flow, instruction privilege levels, and switching between ARM code and THUMB code. -- Three types of data processing instructions which use the on-chip ALU, barrel shifter, and multiplier to perform high-speed data operations in a bank of 31 registers (all with 32-bit register widths). -- Three types of load and store instructions which control data transfer between memory locations and the registers. One type is optimized for flexible addressing, another for rapid context switching, and the third for swapping data. -- Three types of co-processor instructions which are dedicated to controlling external co-processors. These instructions extend the off-chip functionality of the instruction set in an open and uniform way. NOTE All 32-bit ARM instructions can be executed conditionally. The 16-bit THUMB instruction set contains 36 instruction formats drawn from the standard 32-bit ARM instruction set. The THUMB instructions can be divided into four functional groups: -- Four branch instructions. -- Twelve data processing instructions, which are a subset of the standard ARM data processing instructions. -- Eight load and store register instructions. -- Four load and store multiple instructions. NOTE Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with the identical processing model. The 32-bit ARM instruction set and the 16-bit THUMB instruction sets are good targets for compilers of many different high-level languages. When assembly code is required for critical code segments, the ARM programming technique is straightforward, unlike that of some RISC processors which depend on sophisticated compiler technology to manage complicated instruction interdependencies. Pipelining is employed so that all parts of the processor and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.
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S5N8947 DATA SHEET
OPERATING STATES From a programmer's point of view, the ARM7TDMI core is always in one of two operating states. These states, which can be switched by software or by exception processing, are: -- ARM state (when executing 32-bit, word-aligned, ARM instructions), and -- THUMB state (when executing 16-bit, half-word aligned THUMB instructions).
OPERATING MODES The ARM7TDMI core supports seven operating modes: -- User mode: the normal program execution state -- FIQ (Fast Interrupt Request) mode: for supporting a specific data transfer or channel process -- IRQ (Interrupt ReQuest) mode: for general purpose interrupt handling -- Supervisor mode: a protected mode for the operating system -- Abort mode: entered when a data or instruction pre-fetch is aborted -- System mode: a privileged user mode for the operating system -- Undefined mode: entered when an undefined instruction is executed Operating mode changes can be controlled by software, or they can be caused by external interrupts or exception processing. Most application programs execute in User mode. Privileged modes (that is, all modes other than User mode) are entered to service interrupts or exceptions, or to access protected resources. REGISTERS The S5N8947 CPU core has a total of 37 registers: 31 general-purpose 32-bit registers, and 6 status registers. Not all of these registers are always available. Which registers are available to the programmer at any given time depends on the current processor operating state and mode. NOTE When the S5N8947 is operating in ARM state, 16 general registers and one or two status registers can be accessed at any time. In privileged mode, mode-specific banked registers are switched in. Two register sets, or banks, can also be accessed, depending on the core's current state: the ARM state register set and the THUMB state register set: -- The ARM state register set contains 16 directly accessible registers: R0-R15. All of these registers, except for R15, are for general-purpose use, and can hold either data or address values. An additional (seventeenth) register, the CPSR (Current Program Status Register), is used to store status information. -- The THUMB state register set is a subset of the ARM state set. You can access eight general registers, R0R7, as well as the program counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. Each privileged mode has a corresponding banked stack pointer, link register, and saved process status register (SPSR).
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The THUMB state registers are related to the ARM state registers as follows: -- THUMB state R0-R7 registers and ARM state R0-R7 registers are identical -- THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical -- THUMB state SP, LR, and PC map directly to ARM state registers R13, R14, and R15, respectively In THUMB state, registers R8-R15 are not part of the standard register set. However, you can access them for assembly language programming and use them for fast temporary storage, if necessary. EXCEPTIONS An exception arises whenever the normal flow of program execution is interrupted. For example, when processing must be diverted to handle an interrupt from a peripheral. The processor's state just prior to handling the exception must be preserved so that the program flow can be resumed when the exception routine is completed. Multiple exceptions may arise simultaneously. To process exceptions, the S5N8947 uses the banked core registers to save the current state. The old PC value and the CPSR contents are copied into the appropriate R14 (LR) and SPSR register. The PC and mode bits in the CPSR are forced to a value which corresponds to the type of exception being processed. The S5N8947 core supports seven types of exceptions. Each exception has a fixed priority and a corresponding privileged processor mode, as shown in following Table Table 1-3. S5N8947 CPU Exceptions Exception Reset Data Abort FIQ IRQ Prefetch Abort Undefined Instruction SWI Mode on Entry Supervisor Mode Abort Mode FIQ Mode IRQ Mode Abort Mode Undefined Mode Supervisor Mode Priority 1 (highest) 2 3 4 5 6 6 (lowest)
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HARDWARE STRUCTURE
SYSTEM MANAGER Overview The S5N8947 microcontroller's System Manager has the following functions. -- Arbitrates system bus access requests from several master blocks, based on fixed priorities. -- Provides the required memory control signals for external memory accesses. For example, if a master block such as the DMA controller or the CPU generates an address, which corresponds to a DRAM bank, the System Manager's DRAM controller generates the required normal/EDO or SDRAM access signals. The interface signals for normal/EDO or SDRAM can be switched by SYSCFG[31]. -- Provides the required signals for bus traffic between the S5N8947 and ROM/SRAM and the external I/O banks. -- Compensates for differences in bus width for data transfer between the external memory bus and the internal data bus. -- Supports both little and big endian for external memory or I/O devices. Internal registers, however, operate under big-endian mode. -- Supports both motorola mode and intel mode for external I/O devices -- Supports an external bus master with bus request(ExtMREQ) and bus acknowledge(ExtMACK) -- Supports PCMCIA `memory and I/O' master mode System Manager Registers To control external memory operations, the System Manager uses a dedicated set of special registers. By programming the values in the System Manager special registers, you can specify such things as: -- Memory type -- External data access cycle -- External memory and I/O device access cycle -- Memory bank locations -- Size of each memory bank to be used for arbitrary address spacing The System Manager uses special register setting to control the generation and processing of the control signals, addresses, and data that are required by external devices in a standard system configuration. Special registers are also used to control access to ROM/SRAM/Flash banks, a PCMCIA interface, up to four DRAM banks and four external I/O banks, and a special register mapping area. The address resolution for each memory bank base pointer is 64 Kbytes (16 bits). The base address pointer is 10 bits. This gives a total addressable memory bank space of 16 M words.
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0x3FFFFFF Reserved Special register bank Reserved External I/O bank 3 External I/O bank 2 External I/O bank 1 External I/O bank 0 DRAM/SDRAM bank 3 16M words (16M X 32 bits) SA [25:0] DRAM/SDRAM bank 2 DRAM/SDRAM bank 1 DRAM/SDRAM bank 0 PCMCIA bank ROM/SRAM/Flash bank 2 ROM/SRAM/Flash bank 1 ROM/SRAM/Flash bank 0 0x0000000 16K words-4M words (32 bits) ADDR [21:0] 64K bytes-4M bytes (16 bits) ADDR [21:0] Continuous 16K word space for 4 external I/O banks 16K words (fixed)
4K words (Fixed for all I/O banks)
NOTE:
You can define banks anywhere within the 64-Mbyte address space.
Figure 1-7. S5N8947 System Memory Map
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System Memory Map Followings are several important features to note about the S5N8947 system memory map: -- The size and location of each memory bank is determined by the register settings for "current bank base pointer" and "current bank end pointer". You can use this base/next bank pointer concept to set up a consecutive memory map. To do this, you set the base pointer of the "next bank" to the same address as the next pointer of the "current bank". Please note that when setting the bank control registers, the address boundaries of consecutive banks must not overlap. This can be applied even if one or more banks are disabled. -- Four external I/O banks are defined in a continuous address space. A programmer can only set the base pointer for external I/O bank 0. The start address of external I/O bank 1 is then calculated as the external I/O bank 0 start address +16 K. Similarly, the start address for external I/O bank 2 is the external I/O bank 0 start address + 32 K, and the start address for external I/O bank 3 is the external I/O bank 0 start address + 48 K. Therefore, the total consecutive addressable space of the four external banks is defined as the start address of external I/O bank 0 + 64 K bytes. -- Within the addressable space, the start address of each I/O bank is not fixed. You can use bank control registers to assign a specific bank start address by setting the bank's base pointer. The address resolution is 64 K bytes. The bank's start address is defined as "base pointer << 16" and the bank's end address (except for external I/O banks) is "next pointer << 16 - 1". After a power-on or system reset, all bank address pointer registers are initialized to their default values. In this means that a system reset automatically defines ROM bank 0 as a 32-Mbyte space with a start address of zero. This means that, except for ROM bank 0, all banks are undefined following a system startup. The reset values for the next pointer and base pointer of ROM bank 0 are 0x200 and 0x000, respectively. This means that a system reset automatically defines ROM bank 0 as a 32-Mbyte space with a start address of zero. This initial definition of ROM bank 0 lets the system power-on or reset operation pass control to the user-supplied boot code that is stored in external ROM. (This code is located at address 0 in the system memory map.) When the boot code (i.e. ROM program) executes, it performs various system initialization tasks and reconfigures the system memory map according to the application's actual external memory and device configuration. The initial system memory map following system startup is shown in following:
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0x3FFFFFF Special Function Registers 0x3FF0000
Undefined Area 64 M Bytes SA[25:0] ROM/SRAM/FLASH Bank 0 Area (Accessible) 32 M ROM/SRAM/FLASH Bank 0 Area (Accessible) 0x0000000 4 M Address[21:0]
0x2000000
Figure 1-8. Initial System Memory Map (After Reset)
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INSTRUCTION / DATA CACHE The S5N8947 CPU has a unified internal 8-Kbyte instruction/data cache. The cache is configured using two-way, set-associative addressing. The replacement algorithm is pseudo-LRU (Least Recently Used). The cache line size is four words (16 bytes). When a miss occurs, four words must be fetched consecutively from external memory. Typically, RISC processors take advantage of unified instruction/data caches to improve performance.
31 30 29 28 27 26 25 Tag Address (14-bit) Enable non-cacheable control {[28], [24:23]} == 100: Set 0 direct access 101: Set 1 direct access 110: TAG direct access 14
12 11
4
3
21
0
8-bit
2-bit
switch 2
31 30 28
14
15 13
14
0
Height = 256
CS
Set 1 Tag
Set 0 Tag
8-bit Decoder
Tag RAM (32-bit)
Set 1 Icache line = 4 instruction/data (256-bit) Instr3 Instr2 Instr1 Instr0
Set 0 Icache line = 4 instruction/data (256-bit) Instr3 Instr2 Instr1 Instr0
8-bit Height = 256 32-bit 32-bit
2 32 2 (Set 0 Hit) (Set 1 Hit) 32 32
Figure 1-9. Memory Configuration for 8-Kbyte Cache
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I2C BUS CONTROLLER The S5N8947's Internal IC bus (I2C-bus) controller has the following important features: -- It requires only two bus lines, a serial data line (SDA) and a serial clock line (SCL). When the I C-bus is free, both lines are High level. -- Each device that is connected to the bus is software-addressable by a unique address. Slave relationships on 2 the bus are constant. The bus master can be either a master-transmitter or a master-receiver. The I C bus controller supports only single master mode. -- It supports 8-bit, bi-directional, serial data transfers. -- The number of ICs that you can connect to the same I2C-bus is limited only by the maximum bus capacitance of 400 pF. Following figure shows a block diagram of the S5N8947's I2C-bus controller.
2
SDA
Data Control Serial Clock Prescaler 16
Shift buffer register (IICBUF)
SCL
SCL Control
System clock (fMCLK)
Prescaler register (IICPS) 0 BUSY COND1 COND0 ACK LRB IEN BF
Control status register (IICCON)
Figure 1-10. I2C-Bus Block Diagram
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ETHERNET CONTROLLER The S5N8947 has 2-channel Ethernet controllers which operate at either 100/10-Mbits per second in half-duplex or full-duplex mode. In half-duplex mode, the controller supports the IEEE 802.3 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) protocol. In full-duplex mode, it supports the IEEE 802.3 MAC Control Layer, including the Pause operation for flow control. Block Diagram
BDMA+SBUS I/F BDMA Tx Buffer Controller
32
BDMA Tx Buffer (64 words)
32
8 B D I
MAX Tx Buffer (80 bytes)
MAC MAX Tx Buffer Controller M I I / 10 M b p s 7 W i r e
S Y S T E M B U S
Bus Arbiter/ Controller BDMA Rx Buffer (64 words)
32
8
MAX Rx Buffer (16 bytes) Address CAM Interface and comparator
MAX Rx Buffer controller
32
BDMA Rx Buffer Controller
32
CAM Contents Memory (32-words) BDMA control and status register
Flow Controller CRC Checker
32
MAC control and status register
Station Manager
Figure 1-11. Ethernet Controller Block Diagram
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Features and Benefits The most important features and benefits of the S5N8947 Ethernet controller are as follows: -- Cost-effective connection to an external Repeater Interface Controller(RIC)/Ethernet backbone -- Buffered DMA (BDMA) engine using Burst mode -- BDMA Tx/Rx buffers (256 bytes/256 bytes) -- MAC Tx/Rx FIFOs (80 bytes/16 bytes) to support re-transmit after collision without DMA request and to handle DMA latency -- Data alignment logic -- Supports for old and new media (compatible with existing 10-Mbit/s networks) -- Full IEEE 802.3 compatibility for existing applications -- Provides a standard Media Independent Interface (MII) -- Provides an external 7-wire interface, also. -- Station Management (STA) signaling for external physical layer configuration and link negotiation -- On-chip CAM (21 addresses) -- Full-duplex mode for doubled bandwidth -- Pause operation hardware support for full-duplex flow control -- Long packet mode for specialized environments -- Short packet mode for fast testing -- PAD generation for ease of processing and reduced processing time -- Support for old and new media: Compatible with existing 100/10Mbit/s networks. -- Full IEEE 802.3 compatibility: Compatible with existing hardware and software. -- Standard CSMA/CD, Full duplex capability at 100/10 Mbit/s: Increase in data throughput performance.
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SAR AND UTOPIA INTERFACE The S5N8947 provides ATM layer Segmentation and Reassembly (SAR) function over an 8bit UTOPIA interface. The S5N8947 delivers an integrated solution for performing the SAR tasks required to communicate over an ATM network. The device translates packet-based data into 53-byte ATM cells that are asynchronously mapped into various physical media. The S5N8947 can be effectively applied for equipment requiring an interface between packet-based data and ATM-based networks. Block Diagram
Reassembler AAL5, 3/ 4, 0
System I/F and FIFOs
Segmentor AAL5, 3/4, 0
UTOPIA and FIFOs
Scheduler (CBR,UBR,rt-VBR,nrt-VBR)
Registers
Connection Memory (Internal and/or External)
Figure 1-12. SAR Function Block Diagram
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Features and Benefits -- Supports CBR, UBR, rt-VBR and nrt-VBR traffic with rates set on a per-VC or per-VP basis. -- Supports AAL0 (raw cells) and AAL5 segmentation and reassembly. -- Segments and reassembles data up to about 70Mbps via UTOPIA interface. -- Generates and verifies CRC-10 for OAM cells and AAL3/4 cells. -- Supports concurrent OAM cells and AAL5 cells on each active connection. -- Supports simultaneous segmentation and reassembly of up to 32 connections with internal connection memory and up to 4K connections with external system memory. -- On chip 8Kbytes SRAM for internal connection memory. -- Supports Contents Addressable Memory (CAM) for channel mapping (up to 32 connections). -- Supports packet sizes up to 64Kbytes. -- Supports scatter and gather packet capability for large packets. -- Start of Packet offset available for ease of implementing bridging and routing between different protocols. -- Provides glue-less UTOPIA level 2 interface (up to 3 PHYs). -- Supports big and little endian.
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USB CONTROLLER The Universal Serial Bus (USB) is an industry standard bus architecture for computer peripheral attachment. The USB provides a single interface for easy, plug-and-play, hot-plug attachment of peripherals such as keyboard, mouse, speakers, printers, scanners, and communication devices. The USB allows simultaneous use of many different peripherals with a combined transfer rate of up to 12 Mbit/s. The S5N8947 controller includes a highly flexible integrated USB peripheral controller that lets designers implement a variety of microcontroller-based USB peripheral devices for telephony, audio, or other high-end applications. The S5N8947 controller is intended for USB peripherals that use the full-speed signalling rate of 12 Mbit/s. The USB low-speed rate (1.5 Mbit/s) is not supported. An integrated USB transceiver is provided to minimize system device count and cost. The USB peripheral controller's features meet or exceed all of the USB device class resource requirements defined by the USB specification Version 1.0 and 1.1. Consult the USB specification for details about overall USB system design. The integrated USB peripheral controller provides a very efficient and easy-to-use interface, so that device software (or firmware) does not incur the overhead of managing low-level USB protocol requirements. The USB peripheral controller hardware implements a number of USB standard commands directly; the rest can be implemented in device software. In addition, the USB peripheral controller provides a high degree of flexibility to help designers accommodate vendor- or device-class-specific commands, as well as any new features that might be added in future USB specifications. Robust error detection and management features are provided so the device software can manage transfers in any number of ways as required by the application. The USB suspend/resume, reset, and remote wake up features are also supported. Block Diagram
Serial Interface Unit (SIE)
Endpoint 0 FIFO
MCU Address Decoder
MCU / DMA Interface
Endpoint 2 16 in FIFO Serial Interface Engine (SIE) HOST
Endpoint 3 64 out FIFO
Endpoint 4 64 in FIFO
Figure 1-13. USB Module Block Diagram
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DMA CONTROLLER The S5N8947 has a two-channel general DMA controller, called the GDMA. The two-channel GDMA performs the following data transfers without CPU intervention: -- Memory-to-memory (memory to/from memory) -- UART-to-memory (serial port to/from memory) -- SPI-to-memory (SPI port to/from memory) The on-chip GDMA can be started by software and/or by an external DMA request (nXDREQ). Software can also be used to restart a GDMA operation after it has been stopped. The CPU can recognize when a GDMA operation has been completed by software polling and/or when it receives an appropriate internally generated GDMA interrupt. The S5N8947 GDMA controller can increment or decrement source or destination addresses and conduct 8-bit (byte), 16-bit (half-word), or 32-bit (word) data transfers.
System BUS Mode Selection nXDREQ 0 UART SPI GDMA Channel 0 nDREQ nDACK nXDACK 0 GDMA0 Port 14 Data IOPCON [27:26]
GDMA Channel 1 nDREQ nXDREQ 1 Mode Selection nDACK nXDACK 1 GDMA1 IOPCON [29:28] Port 15 Data
Figure 1-14. GDMA Controller Block Diagram
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UART The S5N8947 Universal Asynchronous Receiver/Transmitter (UART) unit provides an asynchronous serial I/O (SIO) port. This can operate in interrupt-based or DMA-based mode. That is, the UART can generate internal interrupts or DMA requests to transfer data between the CPU and the serial I/O port. The most important features of the S5N8947 UART include: -- Programmable baud rates -- Infra-red (IR) transmit/receive -- Insertion of one or two Stop bits per frame -- Selectable 5-bit, 6-bit, 7-bit, or 8-bit data transfers -- Parity checking This unit has a baud rate generator, transmitter, receiver, and a control unit, as shown in next figure. The baudrate generator can be driven by the internal system clock, MCLK. The transmitter and receiver block use this baud rate clock and have independent data buffer registers and data shifters. Transmit data is written first to the transmit buffer register. From there, it is copied to the transmit shifter and then shifted out by the transmit data pin, UATXDn. Receive data is shifted in by the receive data pin, UARXDn. It is then copied from the shifter to the receive buffer register when one data byte has been received. This unit provides software controls for mode selection, and for status and interrupt generation.
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Transmit Buffer Register (UTXBUFn) Baud Rate Divisor (UTBUFn) Baud Rate Generator UATxDn
Transmit Shift Register IR Tx Encoder Line Control Register (ULCONn) UART Control Register (UCONn) UART Status Register (USTATn)
0 1
SYSTEM BUS
nUADTRn nUADSRn Receive Buffer Register (URXBUFn) 0 1 UARxDn IR Rx Decoder
Receive Shift Register
Figure 1-15. UART Block Diagram
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TIMERS The S5N8947 has three 32-bit timers. These timers can operate in interval mode or in toggle mode. The output signals are TOUT0 and TOUT1, respectively. You enable or disable the timers by setting control bits in the timer mode register, TMOD. An interrupt request is generated whenever a timer count-out (down count) occurs. Watchdog timer is also implemented in the S5N8947. The following guidelines apply to watchdog timer functions: -- When a watchdog timer is enabled, it loads a data value to its count register and begins decrementing the count register value by the system clock. -- If the reset from the watchdog timer (WDRESET) reaches to zero, the Watchdog will start its reset sequence. The reset value is then reloaded and the watchdog timer is disabled. -- The WDRESET performs the same function as the External Reset (System Reset) to each block.
32-Bit Timer Data Register (TDATAn) Auto Re-load INTPND and INTMSK fMCLK TMOD.TEn 32-Bit Timer Count Register (TCNTn) [Down Counter] PND Interrupt Request
TMOD.TMDn TMOD.TCLRn
Pulse Generator
TOUTn
Port 16, Port 17 Data Out
IOPCON.TOENn
Figure 1-16. 32-Bit Timer Block Diagram
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I/O PORTS The S5N8947 has 18 programmable I/O ports. You can configure each I/O port to input mode, output mode, or special function mode. To do this, you write the appropriate settings to the IOPMOD, IOPCON0 and IOPCON1 registers. User can set filtering for the input ports using IOPCON0/1 register. Port[0] can be used as nCE1 for PCMCIA interface or SPICLK, port[1] as nCE2 for PCMCIA interface or SPIMOSI, port[2] as nIOIS16 for PCMCIA interface or SPIMISO, port[3] as nALE for PCMCIA interface, port[4] as RW(external data transceiver direction) for PCMCIA interface, or port[7:5] as xINTREQ[2:0] depending on the settings in IOPCON0 register. And port[11:8] can be used as xINTREQ[6:3], port[13:12] as nXDREQ[1:0], port[15:14] as nXDACK[1:0], port[16] as TOUT0, or port[17] as TOUT1 depending on the settings in IOPCON1 register.
IOPMOD IOPCON Alternate Functions Output Latch SYSTEM BUS
VDD
IOPDATA (Write)
IOPDATA (Read) Input Latch Interrupt or DMA Request
Active On/Off & Edge Detection IOPCON
Filter On/Off
Port0/nCE1/SPICLK Port1/nCE2/SPIMOSI Port2/nIOIS16/ SPIMISO Port3/nALE Port4/RW Port5/xINTREQ0 Port6/xINTREQ1 ... Port11/xINTREQ6 Port12/nXDREQ0 Port13/nXDREQ1 Port14/nXDACK0 Port15/nXDACK1 Port16/TOUT0 Port17/TOUT1
IOPCON
Figure 1-17. I/O Port Function Diagram
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INTERRUPT CONTROLLER The S5N8947 interrupt controller has a total of 23 interrupt sources. Interrupt requests can be generated by internal function blocks and external pins. The ARM7TDMI core recongnizes two kinds of interrupts: a normal interrupt request (IRQ), and a fast interrupt request (FIQ). Therefore all S5N8947 interrupts can be categorized as either IRQ or FIQ. The S5N8947 interrupt controller has an interrupt pending bit for each interrupt source. Four special registers are used to control interrupt generation and handling: -- Interrupt priority registers. The index number of each interrupt source is written to the pre-defined interrupt priority register field to obtain that priority. The interrupt priorities are pre-defined from 0 to 22. -- Interrupt mode register. Defines the interrupt mode, IRQ or FIQ, for each interrupt source. -- Interrupt pending register. Indicates that an interrupt request is pending. If the pending bit is set, the interrupt pending status is maintained until the CPU clears it by writing a "1" to the appropriate pending register. When the pending bit is set, the interrupt service routine starts whenever the interrupt mask register is "0". The service routine must clear the pending condition by writing a "1" to the appropriate pending bit. This avoids the possibility of continuous interrupt requests from the same interrupt pending bit. -- Interrupt mask register. Indicates that the current interrupt has been disabled if the corresponding mask bit is "1". If an interrupt mask bit is "0" the interrupt will be serviced normally. If the global mask bit (bit 23) is set to "1", no interrupts are serviced. However, the source's pending bit is set if the interrupt is generated. When the global mask bit has been set to "0", the interrupt is serviced.
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Table 1-4. S5N8947 Interrupt Sources Index Values [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] SPI interrupt I2C-bus interrupt Ethernet controller 1 Rx interrupt Ethernet controller 1 Tx interrupt Ethernet controller 0 Rx interrupt Ethernet controller 0 Tx interrupt SAR Tx/Rx done interrupt SAR Tx/Rx error interrupt USB interrupt GDMA channel 1 interrupt GDMA channel 0 interrupt Timer 2 interrupt Timer 1 interrupt Timer 0 interrupt UART receive and error interrupt UART transmit interrupt External interrupt 6 External interrupt 5 External interrupt 4 External interrupt 3 External interrupt 2 External interrupt 1 External interrupt 0 Interrupt Sources
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SPI The S5N8947 provides a Serial Peripheral Interface (SPI), which is used for register access of other devices, EEPROM and A/D converter. The S5N8947 SPI is full duplex, synchrounous channel and it consists of four signal, receive serial data, transmit serial data, clock and select. Inner clock generator create SPI clock and SPI signals are synchronized with this clock. SPI can be operated with the help of GDMA. So multiple characters can be transmitted and received without host intervention. Otherwise, the host should transmit and receive individual character back-to-back with polling method. SPI does not operate in slave mode and it also cannot be used for multimaster environment. It works with data characters from 4 to 32 bits long. Clock phase and polarity can be configured.
APB BUS
Config Register Command Register GDMA Counter / Control Logic
Transmit Register
Receive Register
33 bits Shift Register
GPIO SPISEL
MCLK
Clock Generator
Pins Interface SPIMISO SPIMOSI SPICLK
Figure 1-18. I/O Block Diagram of SPI (Serial Peripheral Interface)
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SPECIAL FUNCTION REGISTERS
Table 1-5. Speclal Function Registers Group System Manager Registers SYSCFG PCMCON EXTACON0 EXTACON1 EXTDBWTH ROMCON0 ROMCON1 ROMCON2 PCMOFFSET DRAMCON0 DRAMCON1 DRAMCON2 DRAMCON3 REFEXTCON Ethernet1 (BDMA) BDMATXCON BDMARXCON BDMATXPTR BDMARXPTR BDMARXLSZ BDMASTAT CAM BDMATXBUF BDMARXBUF Ethernet1 (MAC) MACON CAMCON MACTXCON MACTXSTAT MACRXCON MACRXSTAT STADATA STACON Offset 0x0000 0x3000 0x3008 0x300C 0x3010 0x3014 0x3018 0x301C 0x3020 0x3024 0x3028 0x302C 0x3030 0x3034 0x9000 0x9004 0x9008 0x900C 0x9010 0x9014 0x91000x917C 0x92000x92FC 0x98000x99FC 0xA000 0xA004 0xA008 0xA00C 0xA010 0xA014 0xA018 0xA01C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description System configuration register PCMCIA Interface control register External I/O timing register 1 External I/O timing register 2 Data bus width for each memory bank ROM/SRAM/Flash bank 0 control register ROM/SRAM/Flash bank 1 control register ROM/SRAM/Flash bank 2 control register PCMCIA bank offset register DRAM bank 0 control register DRAM bank 1 control register DRAM bank 2 control register DRAM bank 3 control register Refresh and external I/O control register Buffered DMA receive control register Buffered DMA transmit control register Transmit trame descriptor start address Receive frame descriptor start address Receive frame maximum size Buffered DMA status CAM content (32 words) BDMA Tx buffer (64 words) for test mode addressing BDMA Rx buffer (64 words) for test mode addressing Ethernet MAC control register CAM control register MAC transmit control register MAC transmit status register MAC receive control register MAC receive status register Station management data Station management control and address Reset/Value 0x23FF0000 0x80000000 0x00000000 0x00000000 0x00000000 0x20000060 0x00000060 0x00000060 0x0000000 0x00000000 0x00000000 0x00000000 0x00000000 0x83FD0000 0x00000000 0x00000000 0x00000000 0x00000000 Undefined 0x00000000 Undefined Undefined Undefined 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008000 0x00000000 0x00006000
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S5N8947 DATA SHEET
Table 1-5. Speclal Function Registers (Continued) Group Ethernet1 (MAC) Registers CAMEN EMISSCNT EPZCNT ERMPZCNT ETXSTAT Ethernet2 (BDMA) BDMATXCON BDMARXCON BDMATXPTR BDMARXPTR BDMARXLSZ BDMASTAT CAM BDMATXBUF BDMARXBUF Ethernet2 (MAC) MACON CAMCON MACTXCON MACTXSTAT MACRXCON MACRXSTAT STADATA STACON CAMEN EMISSCNT EPZCNT ERMPZCNT ETXSTAT Offset 0xA028 0xA03C 0xA040 0xA044 0x9040 0xE000 0xE004 0xE008 0xE00C 0xE010 0xE014 0xE1000xE17C 0xE2000xE2FC 0xE8000xE9FC 0xF800 0xF804 0xF808 0xF80C 0xF810 0xF814 0xF818 0xF81C 0xF828 0xF83C 0xF840 0xF844 0xE040 R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R Description CAM enable register Missed error count register Pause count register Remote pause count register Transmit control frame status Buffered DMA receive control register Buffered DMA transmit control register Transmit trame descriptor start address Receive frame descriptor start address Receive frame maximum size Buffered DMA status CAM content (32 words) BDMA Tx buffer (64 words) for test mode addressing BDMA Rx buffer (64 words) for test mode addressing Ethernet MAC control register CAM control register MAC transmit control register MAC transmit status register MAC receive control register MAC receive status register Station management data Station management control and address CAM enable register Missed error count register Pause count register Remote pause count register Transmit control frame status Reset/Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Undefined 0x00000000 Undefined Undefined Undefined 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008000 0x00000000 0x00006000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
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SAMSUNG ADSL CPE SOLUTION
Table 1-5. Speclal Function Registers (Continued) Group USB FA PM INT INTE FN DFMR DFA DFD E0SC E0SA E0XDS E0LDS E2SC E2SA E2TDS E3SC E3SA E3RDS E4SC E4SA E4TDS SAR SW_RESET GLOBAL_MODE TIMEOUT_BASE TX_READY1 TX_READY2 TX_DONE_ADDR TX_DONE_SIZE RX_POOL0_ADDR Registers Offset 0x7000 0x7004 0x7008 0x700C 0x7010 0x705C 0x7060 0x7064 0x7014 0x7018 0x701C 0x7020 0x7034 0x7038 0x703C 0x7040 0x7044 0x7048 0x7050 0x7054 0x7058 0x8000 0x8008 0x800C 0x8010 0x8014 0x8018 0x801C 0x8020 R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Function address register Power/System management register Interrupt register Interrupt Enable register Frame Number register Direct FIFO access mode register Direct FIFO access address register Direct FIFO access data register Endpoint 0 Status Control register Endpoint 0 DMA Start Address register Endpoint 0 Receive/Transmit Data Size register Endpoint 0 Limit Data Size register Endpoint 2 Status Control register Endpoint 2 DMA Start Address register Endpoint 2 Transmit Data Size register Endpoint 3 Status Control register Endpoint 3 DMA Start Address register Endpoint 3 Transmit Data Size register Endpoint 4 Status Control register Endpoint 4 DMA Start Address register Endpoint 4 Transmit Data Size register Software reset register Global mode register Base multiple for receive packet timeout register Transmit ready first packet or subpacket address Transmit ready last packet or subpacket address Transmit packet done queue base address register Transmit packet done queue size register Receive queue 0 base address register Reset/Value 0x00000000 0x00000000 0x00000000 0x0000041F 0x00000000 0x00000000 0x00000000 0x00000000 0x00005080 0x00000000 0x00000000 0x00800000 0x00005080 0x00000000 0x00000000 0x00000004 0x00000000 0x00000000 0x00005080 0x00000000 0x00000000 0x00000000 0x00000000 0x00FF7FFF 0x00000000 0x00000000 0x00000000 0x00C00000 0x00000000
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S5N8947 DATA SHEET
Table 1-5. Speclal Function Registers (Continued) Group SAR Registers RX_POOL0_SIZE RX_POOL1_ADDR RX_POOL1_SIZE RX_POOL2_ADDR RX_POOL2_SIZE RX_POOL3_ADDR RX_POOL3_SIZE RX_DONE0_ADDR RX_DONE0_SIZE RX_DONE1_ADDR RX_DONE1_SIZE UTOPIA_CONFIG UTOPIA_TIMEOUT CLOCK_RATIO DONE_INT_MASK ERR_INT_MASK DONE_INT_STAT ERR_INT_STAT 1/R_LOOKUP_TBL VP_LOOKUP_TBL UBR_SCH_TBL CBR_SCH_TBL CELL_BUFF SCH_CONN_TBL AAL_CONN_TBL SAR_CONN_TBL CAM_VPVC/CN Offset 0x8024 0x8028 0x802C 0x8030 0x8034 0x8038 0x803C 0x8040 0x8044 0x8048 0x804C 0x8050 0x8054 0x8064 0x8070 0x8074 0x8078 0x807C 0x8080 0x8084 0x8088 0x808C 0x8090 0x8094 0x8098 0x809C 0x81000x81FC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Receive queue 0 size register Receive queue 1 base address register Receive queue 1 size register Receive queue 2 base address register Receive queue 2 size register Receive queue 3 base address register Receive queue 3 size register Receive packet done queue 0 base address register Receive packet done queue 1 base address register UTOPIA interface configuration register UTOPIA interface timeout register Ratio of SAR clock freq toUNI interface speed Interrupt mask for done interrupt register Interrupt mask for error interrupt register Interrupt status for done interrupt register Interrupt status for error interrupt register Base address of 1/Rate lookup table Base address of VP lookup table Base address and entry number of UBR schedule Base address and entry number of CBR schedule Base address and entry number of cell buffer Base address and entry number of scheduler connection table Base address and entry number of AAL connection table Base address and entry number of SAR connection table CAM VPCI, VCI and connection number register Reset/Value 0x00C00000 0x00000000 0x00C00000 0x00000000 0x00C00000 0x00000000 0x00C00000 0x00000000
Receive packet done queue 0 size register 0x00C00000 0x00000000
Receive packet done queue 1 size register 0x00C00000 0x00C00000 0xFFFFFFFF 0x0000008E 0xFFFFFFFF 0xFFFFFFFF 0x00000000 0x00000000 0x00000000 0x00200000 0x0030007F 0x0038007F 0x0040000F 0x0050001F 0x0060001F 0x00700000 0x00000000
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SAMSUNG ADSL CPE SOLUTION
Table 1-5. Speclal Function Registers (Continued) Group SAR Registers CONFIGURATION EXT_CMBASE I/O Ports IOPMOD IOPCON0 IOPCON1 IOPDATA SPI SPICFG SPISTS SPICMD TXCHR RXCHR Interrupt Controller INTMOD INTPND INTMSK INTPRI0 INTPRI1 INTPRI2 INTPRI3 INTPRI4 INTPRI5 INTOFFSET INTPNDPRI INTPNDTST INTOSET_FIQ INTOSET_IRQ I C Bus
2
Offset 0x8200 0x8204 0x5000 0x5004 0x5008 0x500C 0x5804 0x5808 0x580C 0x5810 0x5814 0x4000 0x4004 0x4008 0x400C 0x4010 0x4014 0x4018 0x401C 0x4020 0x4024 0x4028 0x402C 0x4030 0x4034 0XF000 0xF004 0xF008 0xF00C
R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R W R R R/W R/W R/W R
Description Clock control and connection memory configuration register External connection memory base address register I/O port mode register I/O port control 0 register I/O port control 1 register I/O port data register SPI configuration register SPI status register SPI command register SPI transmit register SPI receive register Interrupt mode register Interrupt pending register Interrupt mask register Interrupt priority register 0 Interrupt priority register 1 Interrupt priority register 2 Interrupt priority register 3 Interrupt priority register 4 Interrupt priority register 5 Interrupt offset address register Interrupt pending priority register Interrupt pending test register FIQ interrupt offset register IRQ interrupt offset register I C bus control status register I C bus shift buffer register I C bus prescaler register I C bus prescaler counter register
2 2 2 2
Reset/Value 0x00000046 0x00000000 0x00000000 0x00000000 0x00000000 Undefined 0x0000000F 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00FFFFFF 0x03020100 0x07060504 0x0B0A0908 0x0F0E0D0C 0x13121110 0x00161514 0x0000005C 0x00000000 0x00000000 0x0000005C 0x0000005C 0x00000000 Undefined 0x00000000 0x00000000
IICCON IICBUF IICPS IICCOUNT
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S5N8947 DATA SHEET
Table 1-5. Speclal Function Registers (Continued) Group GDMA Registers GDMACON0 GDMACON1 GDMASRC0 GDMADST0 GDMASRC1 GDMADST1 GDMACNT0 GDMACNT1 UART ULCON UCON USTAT UTXBUF URXBUF UBRDIV Timers TMOD TDATA0 TDATA1 TDATA2 TCNT0 TCNT1 TCNT2 WDCON WDCNT Offset 0xB000 0xC000 0xB004 0xB008 0xC004 0xC008 0xB00C 0xC00C 0xD000 0xD004 0xD008 0xD00C 0xD010 0xD014 0x6000 0x6004 0x6008 0x600C 0x6010 0x6014 0x6018 0x601C 0x6020 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R Description GDMA channel 0 control register GDMA channel 1 control register GDMA source address register 0 GDMA destination address register 0 GDMA source address register 1 GDMA destination address register 1 GDMA channel 0 transfer count register GDMA channel 1 transfer count register UART line control register UART control register UART status register UART transmit holding register UART receive buffer register Baud rate divisor register Timer mode register Timer 0 data register Timer 1 data register Timer 2 data register Timer 0 count register Timer 1 count register Timer 2 count register Watchdog Timer Control register Watchdog Timer Count register Reset/Value 0x00000000 0x00000000 Undefined Undefined Undefined Undefined Undefined Undefined 0xXXXXXX00 0xXXXXXX00 0xXXXXXXC0 Undefined Undefined 0xXXXXXX00 0x00000000 0x00000000 0x00000000 0x00000000 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFF00 0xFFFFFFFF
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SAMSUNG ADSL CPE SOLUTION
ELECTRIC CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS Table 1-6. Absolute Maximum Ratings Parameter Supply Voltage Symbol VDD Rating 1.8V VDD 3.3V VDD DC input Voltage Operating Temperature Storage Temperature VIN T OPR T STG 1.8V input buffer 1.8V interface 3.3V tolerant input buffer - 40 to 85 - 65 to 150 2.7 3.8 2.7 3.8 C C V Units V
RECOMMENDED OPERATING CONDITIONS Table 1-7. Recommaended Operating Conditions Parameter Supply Voltage Symbol VDD/VDDA 1.8V VDD 3.3V VDD Oscillator Frequency External Loop Filter Capacitance Industrial Temperature Range fOSC LF TA 12 320 -40 to 85 Rating 1.8 0.15 3.3 0.3 MHz pF C Units V
Table 1-8. Power Dissipation Parameter Power Dissipation Symbol PD Min Typ 300 Max Units mW
NOTE It is strongly recommended that all the supply pins (VDD/VDDA) be powered from the same source to avoid power latch-up.
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S5N8947 DATA SHEET
DC ELECTRICAL CHARACTERISTICS Table 1-9. DC Electrical Characteristics VDD = 1.8 0.15 V, VEXT = 3.0 0.3V, TA = -40 to 85 C (in case of 3.3V-tolerant I/O) Parameter High level input voltage LVCMOS I/F Low level input voltage Switching threshold Schmitt trigger positive-going threshold Schmitt trigger negative-going threshold High level input current Input buffer Input buffer with pull-up Low level input current Input buffer Input buffer with pull-up High level output voltage Type B1 to B12 Type B1 Type B2 Type B4 Type B6 Low level output voltage Type B1 to B12 Type B1 Type B2 Type B4 Type B6 Tri-state output leakage current Operating current IOZ IOP VOL VOH IOH = - 1 mA IOH = - 1 mA IOH = - 2 mA IOH = - 4 mA IOH = - 6 mA IOL = 1 mA IOL = 1 mA IOL = 2 mA IOL = 4 mA IOL = 6 mA VOUT = VSS or VDD VDD = 1.8V, fMCLK = 72MHz - 10 10 100 ~ 150 A mA 0.45 0.05 V 1.2 ILH VIN = VSS LVCMOS I/F Symbol VIH VIL VT VT+ VT- IIH Conditions - - LVCMOS LVCMOS LVCMOS VIN = VDD Min 1.27 - - - 0.57 - 10 5 - 10 - 40 VDD - 0.05 Typ - - 0.55VDD - - - 18 - - 18 - Max - 0.57 - 1.27 - 10 40 10 -5 - V A Unit V V V - - A
1-47
SAMSUNG ADSL CPE SOLUTION
PACKAGE DIMENSION
This section describes the mechanical data for the S5N8947 208-pin LQFP package.
30.00 0.30 28.00 0.20 0-8
+ 0.10
0.127- 0.05
30.60 0.30
28.00 0.20
208-LQFP-2828
#208
#1 0.50
0.20
+ 0.10 - 0.05
0.08MAX
(1.25)
0.10 0.05 1.40 0.10 1.60MAX 0.10MAX
Figure 1-19. 208-LQFP-2828 Package Dimensions
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0.50 0.20
S5N8950 DATA SHEET
INTRODUCTION
GENERAL DESCRIPTION S5N8950 is an optimized chip of ADSL DMT transceiver supporting G.992.1, G.992.2 and T1.413, and provides a total ADSL DMT chipset solution with AFE chip (S5N8951) for both CO and CPE applications. It supports various interfaces of UTOPIA level 1 and 2 for ATM data, and serial interface for Non-ATM data, and host interface compatible with Motorola and Intel type processors. The S5N8950 is available as 176 LQPF-2424 package. It is fully compatible with G.Lite and G.dmt standards to satisfy interoperability with other chipsets. For CO or CPE application, evaluation tool kits are provided.
ATM Interface S5N8950 ADSL Digital Chip NON-ATM Interface S5N8951 ADSL AFE Chip Hybrid
Telephone Line
Figure 2-1. Samsung ADSL Solution Configuration
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SAMSUNG ADSL CPE SOLUTION
MAIN FEATURES -- Power and performance optimized single port DMT chip. -- Supports ITU-T G.992.1 (G.dmt), G.992.2 (G.Lite) and T1.413 Issue 2 standards. -- Same chip for both ATU-C and ATU-R. -- Supports STM serial interface, and ATM UTOPIA level 1 and level 2 interfaces. -- Flexible host interface for motorola and Intel type controller. -- 14 Bit ADC and DAC interface to AFE. -- Supports all of the framing modes. -- Dual latency paths: fast and interleaved. -- Reed-solomon forward error correction with interleaving. -- 3-D trellis coding and Viterbi algorithm. -- Supports rate adaptive mode. -- Adaptive frequency and time domain equalization. -- Downloadable coefficients of rate-conversion filter banks. -- Supports both the FDM-based and EC-based DMT line coding. -- 0.18 um 1.8 V CMOS technology. -- 3.3V external interface. -- Industrial operation temperature: -40C to 85C. -- 176 LQFP-2424. -- Low power consumption (less than 0.4W). -- Power management. -- ATU-C: DSLAM, Routers at CO. -- ATU-R: Routers at SOHO, stand-alone modems, PC mother boards, and so forth.
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S5N8950 DATA SHEET
SIGNAL INFORMATION
This chapter provides the S5N8950 pin information, e.g., pin configuration, assignment, and description. Figure 2 shows the logical pin configuration of S5N8950. Figure 3 shows the physical pin assignment of S5N8950. Table 1 shows the pin description of S5N8950 according to pin number, while Table 2 shows the I/O driver description of S5N8950. Table 3 summarizes the pin information in terms of interface.
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SAMSUNG ADSL CPE SOLUTION
ATM Interface U_TX_ADDR[4:0] U_TX_DATA[7:0] U_TX_SOC U_TX_ENB U_TX_CLAV U_TX_CLK U_RX_ADDR[4:0] U_RX_ADDR[7:0] U_RX_SOC U_RX_ENB U_RX_CLAV U_RX_CLK
AFE Interface A_AD_DATA[13:0] A_DA_DATA[13:0] A_DA_REF_CLK A_DA_AUX_CLK A_SDI A_AND A_BUSY A_SCLK A_SDO A_SEN A_TX_PWR A_RX_PWR A_RSTN Board Interface B_RSTN B_GP_OUT[1:0] B_GP_IN[1:0] B_BMODE[1:0] B_TMODE B_NMODE
STM Interface S_TX_DAV[1:0] S_TX_CLK[1:0] S_TX_DATA[1:0] S_RX_DAV[1:0] S_RX_CLK[1:0] S_RX_DATA[1:0]
S5N8950
Host Interface H_SEL H_ADDR[9:0] H_DATA[7:0] H_CSN H_RDN H_WRN H_READY H_INT H_WAKEUP B_NTR B_EXT_CLK B_MSC_CLK B_CLK_CNTL
DSP Interface T_MS T_CLK T_DI T_DO T_INTP Power Interface VDD1IH VSS3I VDD3O VSS3O VDD3P VSS3P
PLL Interface P_XTAL_IN P_XTAL_OUT P_PLL_FILTER P_VBBA P_VDD18A1 P_VSS18A1 P_VDD18A2 P_VSS18A2
Figure 2-2. Logical Pin Configuration of S5N8950
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S5N8950 DATA SHEET
A_SDI A_SDO A_SEN VDD1IH VSS3I A_SCLK A_AD_DATA_13 A_AD_DATA_12 A_AD_DATA_11 A_AD_DATA_10 A_AD_DATA_9 A_AD_DATA_8 VDD3O VSS3O A_AD_DATA_7 A_AD_DATA_6 A_AD_DATA_5 A_AD_DATA_4 A_AD_DATA_3 A_AD_DATA_2 A_AD_DATA_1 VDD1IH VSS3I A_AD_DATA_0 A_DA_AUX_CLK A_DA_REF_CLK A_DA_DATA_0 A_DA_DATA_1 A_DA_DATA_2 A_DA_DATA_3 VDD3P VSS3P A_DA_DATA_4 A_DA_DATA_5 A_DA_DATA_6 A_DA_DATA_7 A_DA_DATA_8 A_DA_DATA_9 A_DA_DATA_10 VDD1IH VSS3I A_DA_DATA_11 A_DA_DATA_12 A_DA_DATA_13
133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
A_RSTN A_RX_PWR A_TX_PWR VSS3I A_BUSY VDD1IH A_AND B_MSC_CLK B_CLK_CNTL B_EXT_CLK B_NTR B_NMODE B_BMODE_1 VSS3P B_BMODE_0 VDD3P B_GP_IN_1 B_TMODE B_GP_IN_0 B_RSTN B_GP_OUT_1 VSS3I B_GP_OUT_0 VDD1IH S_RX_DATA_1 S_RX_DAV_1 S_RX_CLK_1 S_TX_DATA_1 S_TX_DAV_1 VSS3O S_TX_CLK_1 VDD3O S_RX_DATA_0 S_RX_DAV_0 S_RX_CLK_0 S_TX_DATA_0 S_TX_DAV_0 S_TX_CLK_0 VSS3I T_INTP VDD1IH T_DO T_DI T_CLK
S5N8950A G.dmt ADSL Transceiver for CO and CPE
T_MS H_DATA_7 H_DATA_6 VSS3I VDD1IH H_DATA_5 H_DATA_4 H_DATA_3 H_DATA_2 H_DATA_1 H_DATA_0 H_ADDR_9 VSS3P VDD3P H_ADDR_8 H_ADDR_7 H_ADDR_6 H_ADDR_5 H_ADDR_4 H_ADDR_3 H_ADDR_2 VSS3I VDD1IH H_ADDR_1 H_ADDR_0 P_XTAL_OUT P_XTAL_IN H_SEL H_WRN VSS3O VDD3O H_WAKEUP H_INT P_VBBA P_VSS18A1 P_VDD18A1 P_PLL_FILTER P_VSS18A2 P_VDD18A2 VSS3I VDD1IH H_RDN H_READY H_CSN
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 U_RX_CLK U_RX_CLAV U_RX_ENB VSS3I U_RX_SOC VDD1IH U_RX_DATA_7 U_RX_DATA_6 U_RX_DATA_5 U_RX_DATA_4 U_RX_DATA_3 VSS3P U_RX_DATA_2 VDD3P U_RX_DATA_1 U_RX_DATA_0 U_RX_ADDR_4 U_RX_ADDR_3 U_RX_ADDR_2 U_RX_ADDR_1 VSS3I U_RX_ADDR_0 VDD1IH U_TX_CLK U_TX_CLAV U_TX_ENB U_TX_SOC U_TX_DATA_7 U_TX_DATA_6 U_TX_DATA_5 VSS3O U_TX_DATA_4 VDD3O U_TX_DATA_3 U_TX_DATA_2 U_TX_DATA_1 U_TX_DATA_0 U_TX_ADDR_4 VSS3I U_TX_ADDR_3 VDD1IH U_TX_ADDR_2 U_TX_ADDR_1 U_TX_ADDR_0
Figure 2-3. Pin Assignment of S5N8950
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SAMSUNG ADSL CPE SOLUTION
Table 2-1. Pin Description of S5N8950 According to Pin Number Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Name U_TX_ADDR_0 U_TX_ADDR_1 U_TX_ADDR_2 VDD1IH U_TX_ADDR_3 VSS3I U_TX_ADDR_4 U_TX_DATA_0 U_TX_DATA_1 U_TX_DATA_2 U_TX_DATA_3 VDD3O U_TX_DATA_4 VSS3O U_TX_DATA_5 U_TX_DATA_6 U_TX_DATA_7 U_TX_SOC U_TX_ENB U_TX_CLAV U_TX_CLK VDD1IH U_RX_ADDR_0 VSS3I U_RX_ADDR_1 U_RX_ADDR_2 U_RX_ADDR_3 U_RX_ADDR_4 U_RX_DATA_0 U_RX_DATA_1 VDD3P U_RX_DATA_2 VSS3P U_RX_DATA_3 U_RX_DATA_4 Type I I I P I P I I I I I P I P I I I I I OZ I P I P I I I I OZ OZ P OZ P OZ OZ Driver PHTICD PHTICD PHTICD VDD1IH PHTICD VSS3I PHTICD PHTICD PHTICD PHTICD PHTICD VDD3O PHTICD VSS3O PHTICD PHTICD PHTICD PHTICD PHTICD PHTOT4 PHTICD VDD1IH PHTICD VSS3I PHTICD PHTICD PHTICD PHTICD PHTOT4 PHTOT4 VDD3P PHTOT4 VSS3P PHTOT4 PHTOT4 Description Utopia Tx address 0 Utopia Tx address 1 Utopia Tx address 2 1.8V internal power supply Utopia Tx address 3 Ground Utopia Tx address 4 Utopia Tx data 0 Utopia Tx data 1 Utopia Tx data 2 Utopia Tx data 3 3.3V pad power supply Utopia Tx data 4 Ground Utopia Tx data 5 Utopia Tx data 6 Utopia Tx data 7 Utopia Tx start of cell Utopia Tx enable Utopia Tx cell available Utopia Tx clock 1.8V internal power supply Utopia Rx address 0 Ground Utopia Rx address 1 Utopia Rx address 2 Utopia Rx address 3 Utopia Rx address 4 Utopia Rx data 0 Utopia Rx data 1 3.3V pad power supply Utopia Rx data 2 Ground Utopia Rx data 3 Utopia Rx data 4
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S5N8950 DATA SHEET
Table 2-1. Pin Description of S5N8950 According to Pin Number (Continued) Pin 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Name U_RX_DATA_5 U_RX_DATA_6 U_RX_DATA_7 VDD1IH U_RX_SOC VSS3I U_RX_ENB U_RX_CLAV U_RX_CLK H_CSN H_READY H_RDN VDD1IH VSS3I P_VDD18A2 P_VSS18A2 P_PLL_FILTER P_VDD18A1 P_VSS18A1 P_VBBA H_INT H_WAKEUP VDD3O VSS3O H_WRN H_SEL P_XTAL_IN P_XTAL_OUT H_ADDR_0 H_ADDR_1 VDD1IH VSS3I H_ADDR_2 H_ADDR_3 H_ADDR_4 Type OZ OZ OZ P OZ P I OZ I I OZ I P P I I O I I I O O P P I I I O I I P P I I I Driver PHTOT4 PHTOT4 PHTOT4 VDD1IH PHTOT4 VSS3I PHTICD PHTOT4 PHTICD PHTICD PHTOT4 PHTICD VDD1IH VSS3I VDD1T_ABB VSS1T_ABB POAR50_ABB VDD1T_ABB VSS1T_ABB VBB1_ABB PHTOT4 PHTOT4 VDD3O VSS3O PHTICD PHTICD PHSOSCM26 PHSOSCM26 PHTICD PHTICD VDD1IH VSS3I PHTICD PHTICD PHTICD Description Utopia Rx data 5 Utopia Rx data 6 Utopia Rx data 7 1.8V internal power supply Utopia Rx start of cell Ground Utopia Rx enable Utopia Rx cell available Utopia Rx clock Chip selection Host CPU Ready Read enable 1.8V internal power supply Ground 1.8V analog power supply 1.8V analog ground PLL capacitor connected to filter 1.8V analog power supply 1.8V analog ground Bulk ground Host interrupt Host wakeup 3.3V pad power supply Ground Host write enable Host type XTAL input for clock XTAL output for clock Host address bus 0 Host address bus 1 1.8V internal power supply Ground Host address bus 2 Host address bus 3 Host address bus 4
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SAMSUNG ADSL CPE SOLUTION
Table 2-1. Pin Description of S5N8950 According to Pin Number (Continued) Pin 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Name H_ADDR_5 H_ADDR_6 H_ADDR_7 H_ADDR_8 VDD3P VSS3P H_ADDR_9 H_DATA_0 H_DATA_1 H_DATA_2 H_DATA_3 H_DATA_4 H_DATA_5 VDD1IH VSS3I H_DATA_6 H_DATA_7 T_MS T_CLK T_DI T_DO VDD1IH T_INTP VSS3I S_TX_CLK_0 S_TX_DAV_0 S_TX_DATA_0 S_RX_CLK_0 S_RX_DAV_0 S_RX_DATA_0 VDD3O S_TX_CLK_1 VSS3O S_TX_DAV_1 S_TX_DATA_1 Type I I I I P P I B B B B B B P P B B I I I OZ P O P O O I O O O P O P O I Driver PHTICD PHTICD PHTICD PHTICD VDD3P VSS3P PHTICD PHTBCDT6SM PHTBCDT6SM PHTBCDT6SM PHTBCDT6SM PHTBCDT6SM PHTBCDT6SM VDD1IH VSS3I PHTBCDT6SM PHTBCDT6SM PHTICD PHTICD PHTICD PHTOT4 VDD1IH PHTOT4 VSS3I PHTOT4 PHTOT4 PHTICD PHTOT4 PHTOT4 PHTOT4 VDD3O PHTOT4 VSS3O PHTOT4 PHTICD Description Host address bus 5 Host address bus 6 Host address bus 7 Host address bus 8 3.3V pad power supply Ground Host address bus 9 Host data bus 0 Host data bus 1 Host data bus 2 Host data bus 3 Host data bus 4 Host data bus 5 1.8V internal power supply Ground Host data bus 6 Host data bus 7 TeakLite JTAG test mode select TeakLite JTAG test clock TeakLite JTAG test input data TeakLite JTAG test output data 1.8V internal power supply TeakLite TJAM interrupt to host Ground Serial Tx clock 0 Serial Tx data valid signal 0 Serial Tx data 0 Serial Rx clock 0 Serial Rx data valid signal 0 Serial Rx data 0 3.3V pad power supply Serial Tx clock 0 Ground Serial Tx data valid signal 1 Serial Tx data 1
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S5N8950 DATA SHEET
Table 2-1. Pin Description of S5N8950 According to Pin Number (Continued) Pin 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Name S_RX_CLK_1 S_RX_DAV_1 S_RX_DATA_1 VDD1IH B_GP_OUT_0 VSS3I B_GP_OUT_1 B_RSTN B_GP_IN_0 B_TMODE B_GP_IN_1 VDD3P B_BMODE_0 VSS3P B_BMODE_1 B_NMODE B_NTR B_EXT_CLK B_CLK_CNTL B_MSC_CLK A_AND VDD1IH A_BUSY VSS3I A_TX_PWR A_RX_PWR A_RSTN A_SDI A_SDO A_SEN VDD1IH VSS3I A_SCLK A_AD_DATA_13 A_AD_DATA_12 Type O O O P O P O I I I I P I P I I B I I I I P I P O O O I O O P P O I I Driver PHTOT4 PHTOT4 PHTOT4 VDD1IH PHTOT4 VSS3I PHTOT4 PHTISD PHTICD PHTICD PHTICD VDD3P PHTICD VSS3P PHTICD PHTICD PHTBCDT6SM PHTICD PHTICD PHTICD PHTICD VDD1IH PHTICD VSS3I PHTOT4 PHTOT4 PHOB2 PHICD PHOB2 PHOB2 VDD1IH VSS3I PHOB2 PHICD PHICD Description Serial Rx clock 1 Serial Rx data valid signal 1 Serial Rx data 1 1.8V internal power supply General purpose output 0 Ground General purpose output 1 System reset General purpose input 0 Test Mode General purpose input 3.3V pad power supply TeakLite boot mode selection Ground TeakLite boot mode selection NAND tree test mode ATM Network Timing Reference External clock Clock control signal Misc. clock for BIRA test Audible noise detection 1.8V internal power supply AFE busy signal Ground TX line driver power enable RX line driver power enable AFE reset AFE serial input data AFE serial output data AFE serial enable 1.8V internal power supply Ground AFE serial clock ADC data 13 ADC data 12
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SAMSUNG ADSL CPE SOLUTION
Table 2-1. Pin Description of S5N8950 According to Pin Number (Continued) Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 Name A_AD_DATA_11 A_AD_DATA_10 A_AD_DATA_9 A_AD_DATA_8 VDD3O VSS3O A_AD_DATA_7 A_AD_DATA_6 A_AD_DATA_5 A_AD_DATA_4 A_AD_DATA_3 A_AD_DATA_2 A_AD_DATA_1 VDD1IH VSS3I A_AD_DATA_0 A_DA_AUX_CLK A_DA_REF_CLK A_DA_DATA_0 A_DA_DATA_1 A_DA_DATA_2 A_DA_DATA_3 VDD3P VSS3P A_DA_DATA_4 A_DA_DATA_5 A_DA_DATA_6 A_DA_DATA_7 A_DA_DATA_8 A_DA_DATA_9 A_DA_DATA_10 VDD1IH VSS3I A_DA_DATA_11 Type I I I I P P I I I I I I I P P I O O O O O O P P O O O O O O O P P O Driver PHICD PHICD PHICD PHICD VDD3O VSS3O PHICD PHICD PHICD PHICD PHICD PHICD PHICD VDD1IH VSS3I PHICD PHOB2 PHOB2 PHOB2 PHOB2 PHOB2 PHOB2 VDD3P VSS3P PHOB2 PHOB2 PHOB2 PHOB2 PHOB2 PHOB2 PHOB2 VDD1IH VSS3I PHOB2 ADC data 11 ADC data 10 ADC data 9 ADC data 8 3.3V pad power supply Ground ADC data 7 ADC data 6 ADC data 5 ADC data 4 ADC data 3 ADC data 2 ADC data 1 1.8V internal power supply Ground ADC data 0 DAC data auxiliary clock DAC data reference clock DAC data 0 DAC data 1 DAC data 2 DAC data 3 3.3V pad power supply Ground DAC data 4 DAC data 5 DAC data 6 DAC data 7 DAC data 8 DAC data 9 DAC data 10 1.8V internal power supply Ground DAC data 11 Description
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S5N8950 DATA SHEET
Table 2-1. Pin Description of S5N8950 According to Pin Number (Continued) Pin 175 176 Name A_DA_DATA_12 A_DA_DATA_13 Type O O Driver PHOB2 PHOB2 DAC data 12 DAC data 13 Description
Table 2-2. I/O Driver Description of S5N8950 Pad PHTICD PHISD PHSCKDSD PHTISD PHICD PHOB2 PHTOT4 PHTBCDT6SM VDD1IH VSS3I VDD3O VSS3O VDD3P VSS3P I/O I I I I I O OZ B I I I I I I Description 5V tolerant for 3.3V interface LVCMOS level input buffer with pull-down 3.3V interface LVCMOS Schmitt-Trigger level input buffer with pull-down 3.3V LCMOS Schmitt Trigger level input clock driver pull-down. 5V tolerant for 3.3V interface LVCMOS Schmitt-Trigger level input buffer with pull-down 3.3V interface LVCMOS level input buffer with pull-down 3.3V LVCMOS normal output buffer driving 2mA 5V tolerant for 3.3V interface tri-state output buffer driving 4mA 3.3V interface 5V tolerant LVCMOS level tri-state bi-directional buffer driving 6mA medium slew rate control with pull-down VDD for 1.8V internal power in the near by 3.3V pad. VSS for 1.8V internal power in the near by 3.3V pad. VDD for 3.3V output driver power VSS for 3.3V output driver power VDD for 3.3V pre- driver power VSS for 3.3V pre- driver power
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SAMSUNG ADSL CPE SOLUTION
Table 2-3. Pin Summary in Terms of Interface Name UTOPIA Interface U_TX_ADDR[4:0] U_TX_DATA[7:0] U_TX_SOC U_TX_ENB U_TX_CLAV U_TX_CLK U_RX_ADDR[4:0] U_RX_DATA[7:0] U_RX_SOC U_RX_ENB U_RX_CLAV U_RX_CLK STM Interface S_TX_DAV[1:0] S_TX_CLK[1:0] S_TX_DATA[1:0] S_RX_DAV[1:0] S_RX_CLK[1:0] S_RX_DATA[1:0] Host Interface H_SEL H_ADDR[9:0] H_DATA[7:0] H_CSN H_RDN H_WRN H_READY H_INT H_WAKEUP I I B I I I OZ O O PHTICD PHTICD PHTBCDT6SM PHTICD PHTICD PHTICD PHTOT4 PHTOT4 PHTOT4 Host type: [0]=Motorola / [1]= Intel Host address bus [9:0] Host data bus [7:0] Chip selection Not used. Read enable: active low Motorola: [0]=write enable / [1]=read enable Intel: Write enable: active low Motorola: Host CPU DTACK - active low Intel: Host CPU Ready - active high Motorola: Interrupt IRQ - active low Intel: Interrupt INT - active high Host wakeup O O I O O O PHTOT4 PHTOT4 PHTICD PHTOT4 PHTOT4 PHTOT4 Serial Tx data valid signal [1:0] Serial Tx clock [1:0] Serial Tx data [1:0] Serial Rx data valid signal [1:0] Serial Rx clock [1:0] Serial Rx data [1:0] I I I I OZ I I OZ OZ I OZ I PHTICD PHTICD PHTICD PHTICD PHTOT4 PHTICD PHTICD PHTOT4 PHTOT4 PHTICD PHTOT4 PHTICD Utopia Tx address [4:0] Utopia Tx data [7:0] Utopia Tx start of cell Utopia Tx enable Utopia Tx cell available Utopia Tx clock, 25MHz Utopia Rx address [4:0] Utopia Rx data [7:0] Utopia Rx start of cell Utopia Rx enable Utopia Rx cell available Utopia Rx clock, 25MHz Type Driver Function
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S5N8950 DATA SHEET
Table 2-3. Pin Summary in Terms of Interface (Continued) Name AFE Interface A_AD_DATA[13:0] A_DA_DATA[13:0] A_DA_REF_CLK A_DA_AUX_CLK A_SDI A_SCLK A_SDO A_SEN A_RSTN A_BUSY A_AND A_TX_PWR A_RX_PWR Board Interface B_RSTN B_GP_OUT[1:0] B_GP_IN[1:0] B_BMODE[1:0] I O I I PHTISD PHTOT4 PHTICD PHTICD System reset (active low) General purpose output General purpose input TeakLite boot mode selection [0] = simple reset [1] = boot from Host CPU (normal mode) [2] = boot from JTAG (emulation mode) [3] = self-booting (test mode) Test Mode Enable [0] Normal [1] Test mode NAND tree test mode [0] NAND tree test mode [1] Normal ATM network timing reference External clock for test mode Misc. clock for test mode Clock control signal [0] = 8950 uses PLL clocks. [1] = 8950 uses external clocks. Interface DSP JTAG test mode select I O O O I O O O O I I O O PHICD PHOB2 PHOB2 PHOB2 PHICD PHOB2 PHOB2 PHOB2 PHOB2 PHTICD PHTICD PHTOT4 PHTOT4 ADC data DAC data DAC data reference clock DAC data auxiliary clock (Not Used) AFE serial input data AFE serial clock AFE serial output data AFE serial enable (active low) AFE reset (active low) AFE busy (active high) / TL 2-nd interrupt Audible noise detection (active high) TX line driver power enable (active high) RX line driver power enable (active high) Type Driver Function
B_TMODE
I
PHTICD
B_NMODE
I
PHTICD
B_NTR B_EXT_CLK B_MSC_CLK B_CLK_CNTL
B I I I
PHTBCDT6SM PHTICD PHTICD PHTICD
DSP JTAG T_MS I PHTICD
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SAMSUNG ADSL CPE SOLUTION
Table 2-3. Pin Summary in Terms of Interface (Continued) Name T_CLK T_DI T_DO T_INTP PLL Interface P_XTAL_IN P_XTAL_OUT P_PLL_FILTER P_VDD18A2 P_VSS18A2 P_VDD18A1 P_VSS18A1 P_VBBA Power Interface VDD1IH VSS3I VDD3O VSS3O VDD3P VSS3P I I I I I I VDD1IH VSS3I VDD3O VSS3O VDD3P VSS3P 1.8V internal power in the near by 3.3V pad. 1.8V internal ground in the near by 3.3V pad. 3.3V output-driver power 3.3V output-driver ground 3.3V pre-driver power 3.3V pre-driver ground I O O I I I I I POAR50_ABB VDD1T_ABB VSS1T_ABB VDD1T_ABB VSS1T_ABB VBB1_ABB PHSOSCM26 XTAL input for clock. XTAL output for clock. Internal PLL pump out connected to filter 1.8V digital power supply 1.8V digital ground 1.8V analog power supply 1.8V analog ground Bulk ground Type I I OZ O Driver PHTICD PHTICD PHTOT4 PHTOT4 Function DSP JTAG test clock DSP JTAG test input data DSP JTAG test output data DSP JTAG interrupt to host
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S5N8950 DATA SHEET
FUNCTION DESCRIPTION
OVERVIEW The G.dmt ADSL system consists of two main chips; G.dmt ADSL transceiver chip (S5N8950) and Analog Front End chip (S5N8951). The AFE provides an analog interface with the line drivers and hybrid components to connect the PSTN network. S5N9850 provides all the digital functions of the G.dmt as depicted in Figure 4.
Framer/de-Framer
UTOPIA interface
DMT Modulator
Channel Encoder
Interpolator
AFE Tx interface
TC
Echo canceller DMT Demodulator
Serial interface
Channel Decoder
Decimator
AFE Rx interface
Control Bus
Host interface JTAG interface UART interface TeakLite DSP core SRAM for Program & Data
PLL
Figure 2-4. Block Diagram
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SAMSUNG ADSL CPE SOLUTION
The input bit stream is divided into bit slices in Framer/de-Framer module, and they are fed into the DMT modulator, which are allocated to 256 sub-channels according to the bit-loading table. The bit slices are then converted to frequency-domain complex samples by the QAM encoder. The 256 complex samples are changed to 512 time-domain samples by IFFT in the DMT modulator. The Tx filter in the Interpolator module performs band separation and interpolation functions. The received signals are attenuated and distorted in terms of both phase and amplitude. PLL fixes the phase errors using the pilot-tone transmitted from the CO side. The synchronization recovery algorithm uses a known synchronization symbol defined in the standard for frame synchronization. The TEQ in the Decimator module is a filter that adaptively alters the channel so that the impulse response is reduced to the length of the cyclic prefix, which will be removed prior to FFT in the DMT demodulator module. The FEQ in the DMT demodulator module is a one tap complex adaptive filter for each sub-channel, which adjusts the gains and phases of the received signals. The equalizers are adaptively updated due to the transmission channel environment. In FDM-based DMT modulation, the frequency band, 0 to 1.104MHz, is divided into 256 equally spaced subchannels, of which 26kHz (#6) to 134kHz (#31) is allocated for the upstream, and 142kHz (#33) to 1.100MHz (#255) for the downstream. The Nyquist rate of the downstream and upstream, therefore, should be 2.208MHz and 276kHz, respectively. DMT inherently transmits an optimized time-variable spectrum. This spectrum is adjusted according to the desired data rate and the transmission characteristics (transfer function and noise spectrum) on each and every sub-channel. For this, CO and CPE transmit pseudo random signals defined in the standard to each other during initialization. They measure the quality of each of these received signals and then decide whether a tone has sufficient quality to be used for further transmission and, if so, how much data this tone should carry relative to the other tones that are used. They inform the bit loading result to each other. SUB-MODULE FUNCTIONAL DESCRIPTION DMT Modulator/Demodulator QAM Encoder and Decoder An algorithmic constellation encoder shall be used to construct constellations. Data bits from the DMT symbol buffer shall be extracted and these bits form a binary word {Vb-1, Vb-2, ... , V1, V0}. The first bit extracted shall be V0, the LSB. For a given sub-channel, the encoder shall select an odd-integer point (X, Y) from the square-grid constellation based on the b bits. For example, for b=2, the four constellation points are labeled 0, 1, 2, 3 corresponding to (V1, V0) = (0, 0), (0, 1), (1, 0), (1, 1), respectively. Gain-Scaling For the transmission of data symbols, gain-scaling factors, gi, shall be applied to all tones as requested by the ATU-R and possibly updated during show-time via the bit swap procedure. If bi > 0 then only values of gi within a range of approximately 0.75 to 1.33 (i.e., 0 +/- 2.5dB) may be used to equalize the expected error rates for all data-carrying sub-channels. If bi = 0, then only gi values of 0 or 1 may be used. During synchronization no gain scaling shall be applied to any tone. Each point, (Xi, Yi), or complex number, Zi = Xi + jYi, output from the encoder is multiplied by gi: Zi' = giZl
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S5N8950 DATA SHEET
IFFT/FFT The FFT/IFFT performs DMT modulation and demodulation simultaneously. In the TX path, the IFFT operation makes the Hermitian Symmetry of the DMT symbol in the frequency domain and transforms into a time domain representation. In the RX path, the FFT operation transforms the time-domain DMT symbol into a frequency domain representation. Frequency-Domain Equalizer (FEQ) Since each sub-channel output of the FFT will be scaled in magnitude and offset in phase by the values of the channel transfer function at the corresponding center frequency for the tone, FEQ will be adaptively scale each sub-channel by the inverse of the channel gain and phase so that common decision boundary can be used in decoding the constellations. The FEQ is a one-tap complex adaptive filter for each sub-channel. Interpolator/Decimator Interpolation Filter Interpolation filter is in front of DAC in transmitter. It is used to interpolate the filter input signal, which is zerosinserted between filter input data samples, and remove the mirror image of the interpolated signals. Therefore the sampling rate becomes higher. By using interpolation filter, the analog filter next to DAC can be low-order and easily implemented. Decimation Filter Decimation filter is next to ADC in receiver. It is used to remove the mirror image of the received signals and decimate the filter input signal, which is over-sampled in ADC. Therefore the filter output signal becomes Nyquist rate. By using over-sampling and decimation, the analog filter in front of ADC can be low-order and easily implemented. Time-Domain Equalizer (TEQ) The Time domain Equalizer (TEQ) is a filter to shorten channel so that the effective length of the channel impulse response is reduced to the length of the cyclic prefix or less in a minimum-mean-square distortion sense. If channel impulse response is very short, zero inter-channel-interference can be achieved by appending to each block of samples of transmit signal a cyclic prefix (CP) that is the same length as the shortened impulse response, but impulse responses of most practical channels are much longer than the CP length. One solution is to use the TEQ for shortening the channel impulse response
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SAMSUNG ADSL CPE SOLUTION
Channel Encoder/Decoder CRC Generator and CRC Checker CRC (cyclic redundancy check) is used extensively in detecting transmission error over a channel. Two cyclic redundancy checks - one for the fast data buffer and one for the interleaved data buffer - are generated for each super-frame and transmitted in the first frame of the following super-frame. At the receiver, CRC is generated for the one super-frame, and then CRC checker compares the resulting CRC and the CRC received in the first frame of next super-frame. Scrambler and De-scrambler The scrambler is used to randomize the binary data stream output from the fast and interleaved data buffers. This ensures that random data is transmitted even when constant data is applied to the system. The scrambler transforms input stream by XORing the data with a 18th and 24th previous data. The de-scrambler accepts the error protected data stream output from the Reed-Solomon decoder and perform de-scrambling by reversing the function of the scrambler at the transmitter. Reed Solomon Encoder and Decoder The RS CODEC is used to detect and correct the errors imposed on a channel. The decoder is programmable and the programmable parameter are codeword length N (1 N 255), and redundancy R (R = 0, 2, 4, 6, 8, 10, 12, 14, 16 ). Interleaver and De-interleaver The function of the interleaver is to rearrange the input bit stream into different order. The programmable interleaver depths D are 1, 2, 4, 8, 16, 32, and 64. The de-interleaver is supposed to reverse that process and restore the original order of the sequence. Framer and De-framer The Framer/De-framer in S5N8950 supports ITU-T Recommendation G.992.1, G.992.2 and T1.413 frame structure, EOC/AOC insertion/extraction, and NTR (Network Timing Reference) at ATU-C. The framer generates super-frame structure as defined in G.992.1, G.992.2, and T1.413 standards. The single latency mode, dual latency mode and four framing modes are fully supported. The EOC/AOC and the payload data are inserted in the super-frame structure by the framer and are extracted from the super-frame structure by the de-framer. Cell TC HEC Generation The HEC byte is generated in the transmit direction as described in ITU-T Recommendation I.432, including the recommended modulo 2 addition of pattern 01010101 to the HEC bits. The generator polynomial coefficient set used and the HEC sequence generation procedure is in accordance with ITU-T Recommendation I.432.
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S5N8950 DATA SHEET
Idle Cell Insertion Idle cells are inserted in the transmit direction for cell rate decoupling. Cell TC discards the idle cells at the receiver modem. Scrambling Scrambling of the cell payload field is used in the transmit direction to improve the security and robustness of the HEC cell delineation mechanism. In addition, it randomizes the data in the information field, for possible improvement of the transmission performance. The self-synchronizing scrambler polynomial procedures defined in the ITU-T Recommendation I.432 are implemented. Cell Delineation The identification of cell boundaries in the payload is performed using a coding law checking the HEC field in the cell header according to the algorithm described in the ITU-T Recommendation I.432.
x 43 + 1 and
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SAMSUNG ADSL CPE SOLUTION
INTERFACE
UTOPIA INTERFACE S5N8950 provides both UTOPIA level 1 and 2 interfaces for ATM data. The UTOPIA interface is designed to run at maximum 25MHz. While UTOPIA level 1 supports only one PHY device, while UTOPIA level 2 supports multiPHY devices, which is accomplished by a single pair of handshake signals for each direction, e.g., U_TX_ENB/U_TX_CLAV for data transmission and U_RX_ENB/U_RX_CLAV for data reception. The U_TX_ADDR and U_RX_ADDR are used to distinguish between ports, using a register per port to set a specific address match. Internally each port is handled separately with independent data buffers, to avoid any queue blocking problems. In S5N8950, two ports for UTOPIA level 2 interface are provided and two registers for each port, TC.CFG[0] and TC.CFG [1], are used for matching a unique address to port. In the Tx direction, when a channel address is detected on the U_TX_ADDR, the U_TX_CLAV signal is driven to indicate whether or not the channel has room to accept a new cell. The U_TX_ADDR is also sampled on the falling edge of U_TX_ENB to select a channel for cell transfer. The Rx interface is similar in operation and timing, when a channel address is detected on the U_RX_ADDR, the U_RX_CLAV signal is driven to indicate if a received cell is available to be read. On the falling edge of U_RX_ENB, the U_RX_ADDR is sampled to select a channel for a received cell. If a channel is scanned too slowly in the Rx direction or a channel is not scanned for a long time, cell overrun may occur causing cells to be discarded. Loss of cells in overrun conditions is recorded in the status register, TC.CELL_LOSS_CNT[1/0]. The number of discarded cell by HEC error is recorded in the status register, TC.HEC_ERR_CNT[1/0]. STM INTERFACE S5N8950 has a STM interface for serial data transmission. It supports envelope and indicate modes for 3-pin STM interface, and 2-pin STM interface. The STM interface is designed to run at maximum 17 MHz. The bit rate in STM transmission mode is restricted to maximum 8 Mbps, while that in ATM mode is maximum 12 Mbps.
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S5N8950 DATA SHEET
HOST INTERFACE S5N8950 has an asynchronous parallel bus slave interface in operation with Motorola MC68000 bus type or Intel 8086 bus type. Thus, S5N8950 is controlled and configured by an external host processor across the host interface. Two interface types are supported: Motorola and Intel type interfaces. The H_SEL pin makes the choice: 0 and 1 select Motorola and Intel type interfaces, respectively. The interface circuit with MC68000 processor or Intel 8086 is quite simple. The ATU-C and ATU-R control interface between MC68000 or 8086 and S5N8950 uses an 8-bit data bus and a 10-bit address bus as illustrated in Figure 5 or Figure 6. The host processor is only permitted to access registers by byte size, while S5N8950 control program should access by word size, that is, 16 bits. In case of 32 bit processor interface like MPC860, the chip select must be programmed as a 8-bits so that dynamic bus sizing and correct word steering occurs.
MC86000 or MPC860
S5N8950 CS* R/W* 45 60
H_CSN
H_WRN
DS*/OE* ADDR[9:0]
47
H_RDN
H_ADDR[9:0]
DATA[7:0] DTACK* VCC 61 46
H_DATA[7:0]
H_READY
H_SEL
1K
GND
Figure 2-5. MC68000 Bus Type Processor Interface Circuit Diagram
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SAMSUNG ADSL CPE SOLUTION
I8086 or S5N8947 CS* WR* 44 60 H_CSN
S5N8950
H_WRN
RD* ADDR[10:1]
47
H_RDN
H_ADDR[9:0]
DATA[15:0] RDY 46
H_DATA[7:0]
H_READY 61 VCC
H_SEL
Figure 2-6. Intel 8086 Bus Type Processor Interface Circuit Diagram
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S5N8950 DATA SHEET
AFE INTERFACE The AFE interface signals of the S5N8950 are categorized into two parts. The first is TX and RX data path signals. And the other is an AFE serial control signal. The TX and RX data path signals are ADC and DAC signals synchronized to the A_DA_REF_CLK signal. The AFE serial control interface consists of an active-low enable output pin (A_SEN), a serial clock output pin (A_SCLK), a data output pin (A_SDO), a data input pin (A_SDI), additional AFE busy status input pin (A_BUSY), and AFE chip reset output pin (A_RSTN). S5N8950 can access AFE registers with these signals. And all the ADSL physical operation is performed by the S5N8950, so the AFE chip is controlled by the S5N8950. Figure shows the AFE interface circuit diagram between S5N8950 and S5N8951.
S5N8950
AFE S5N8951 TX_DATA[13:0] RX_DATA[13:0] 158 135 138 134 133 128 132 NC 48 RESET 6 45 44 47 46 MCLK SEN SCLK SDIN(*) SDOUT(*)
A_DA_DATA[13:0] A_AD_DATA[13:0] A_DA_REF_CLK A_SEN A_SCLK (*)A_SDO (*)A_SDI A_BUSY A_RSTN
Figure 2-7. AFE Interface Circuit Diagram Please keep in mind that A_SDO signal of S5N8950 must be connected with SDIN signal of S5N8951 and A_SDI signal of S5N8950 must be connected with SDOUT signal of S5N8951.
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SAMSUNG ADSL CPE SOLUTION
TIMING INFORMATION
AFE INTERFACE Data Path
tPWH A_DA_REF_CLK tSU(1) tD(1) A_AD_DATA[13:0] (4.416MHz) tD(2) A_DA_DATA[13:0] (4.416MHz)
tPWL
tH(1)
tSU(2)
tH(2)
Figure 2-8. Timing Diagram of Data Path Signals Between S5N8950 and S5N8951
Table 2-4. Timing Values of Data Path Signals Between S5N8950 and S5N8951 Parameter A_AD_DATA delay after A_DA_REF_CLK A_AD_DATA setup time to A_DA_REF_CLK A_AD_DATA hold time after A_DA_REF_CLK A_DA_DATA delay after A_DA_REF_CLK A_DA_DATA setup time to A_DA_REF_CLK A_DA_DATA hold time after A_DA_REF_CLK A_DA_REF_CLK high time A_DA_REF_CLK low time Symbol tD(1) tSU(1) tH(1) tD(2) tSU(2) tH(2) tPWH tPWL Min 0 10 10 0 10 10 112 112 10 Typ Max 10 Unit ns ns ns ns ns ns ns ns
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S5N8950 DATA SHEET
Serial Control Path
tCYC tD(1) A SEN A SCLK tD(3) A SDO tSU(1) A SDI tH(1) tPWH tPWL
tD(2) tPW
Figure 2-9. Timing Diagram of AFE Control Interface
Table 2-5. Timing Values of AFE Control Interface Parameter A_SCLK period A_SCLK high time A_SCLK low time A_SCLK delay after A_SEN A_SEN delay after A_SCLK A_SDO delay after A_SCLK A_SDI setup time to A_SCLK A_SDI hold time after A_SCLK A_SEN pulse width Symbol tCYC tPWH tPWL tD(1) tD(2) tD(3) tSU(1) tH(1) tPW 0 10 10 896 Min Typ 896 448 448 784 112 10 Max Unit ns ns ns ns ns ns ns ns ns
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SAMSUNG ADSL CPE SOLUTION
HOST BUS INTERFACE Write Cycle Timing of Motorola Type Interface
H_ADDR[9:0]
H_DATA[7:0] tSU(1) H_CSN tSU(2) H_WRN (RD/WRN) tD(2) H_READY (DTACKN) MCLK (Internal_CLK) tD(1) tPW tH
tF
Figure 2-10. Write Cycle Timing of Motorola MC68000 Type Bus Interface
Table 2-6. Write Timing Value of Motorola MC68000 Type Bus Interface Parameter H_ADDR setup time to H_CSN H_WRN setup time to H_CSN H_DATA valid data after H_CSN H_READY delay after H_CSN H_DATA hold time after H_CSN H_READY float time to tri-state after H_CSN H_CSN pulse width Symbol tSU(1) tSU(2) tD(1) tD(2) tH tF tPW 0 1 168 10 Min 0 0 50 112 Typ Max Unit ns ns ns ns ns ns ns
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S5N8950 DATA SHEET
Read Cycle Timing of Motorola Type Interface
H_ADDR[9:0]
H_DATA[7:0] tSU(1) tH H_CSN tSU(2) tPW
H_WRN (RD/WRN) H_READY (DTACKN) MCLK (Internal_CLK)
tD(1)
tD(2)
tF
Figure 2-11. Read Cycle Timing of Motorola MC68000 Bus Type Interface
Table 2-7. Read Cycle Timing Values of Read Cycle of Motorola Type Bus Interface Parameter H_ADDR setup time to H_CSN H_WRN setup time to H_CSN H_READY delay after H_CSN H_DATA valid data after H_READY H_DATA hold time after H_CSN H_READY float time to tri-state after H_CSN H_CSN pulse width Symbol tSU(1) tSU(2) tD(1) tD(2) tH tF tPW 0 1 168 10 Min 0 0 112 0 Typ Max Unit ns ns ns ns ns ns ns
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SAMSUNG ADSL CPE SOLUTION
Write Cycle Timing of Intel Type Interface
H ADDR[9:0]
H DATA[15:0] tSU(1) H CSN tSU(2) H WRN tD(2) H READY tPW(2) tPW(1) tH tD(1)
tF
MCLK
Figure 2-12. Write Cycle Timing of Intel 8086 Bus Type Interface
Table 2-8. Write Cycle Timing Values of Intel 8086 Bus Type Interface Parameter H_ADDR setup time to H_CSN H_CSN setup time to H_WRN H_DATA valid data after H_WRN H_READY delay after H_WRN H_DATA float time to tri-state after H_WDN H_DATA hold time after H_WRN H_WRN pulse width H_READY pulse width Symbol tSU(1) tSU(2) tD(1) tD(2) tF tH tPW(1) tPW(2) 0 0 168 168 280 Min 0 0 50 10 Typ Max Unit ns ns ns ns ns ns ns ns
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S5N8950 DATA SHEET
Write Cycle Timing of Intel Type Interface
H ADDR[9:0]
H DATA[15:0] tSU(1) H CSN tSU(2) H RDN tD(2) H READY tPW(2) tPW(1) tH tD(1) tF
MCLK
Figure 2-13. Read Cycle Timing of Intel 8086 Bus Type Interface
Table 2-9. Read Cycle Timing Values of Intel 8086 Bus Type Interface Parameter H_ADDR setup time to H_CSN H_CSN setup time to H_RDN H_DATA valid data after H_RDN H_READY delay after H_RDN H_DATA float time to tri-state after H_RDN H_CSN hold time after H_RDN H_RDN pulse width H_READY pulse width Symbol tSU(1) tSU(2) tD(1) tD(2) tF tH tPW(1) tPW(2) 0 0 0 168 168 280 Min 0 0 168 10 Typ Max Unit ns ns ns ns ns ns ns ns
2-29
SAMSUNG ADSL CPE SOLUTION
STM INTERFACE Indicate Mode in STM Interface
t1 S_TX_CLK t2 S_TX_DAV t3 S_TX_DATA S_RX_CLK t2 S_RX_DAV S_RX_DATA D0 D1 D2 D3 D4 D5 D6 D7 t4 D0 D1 D2 D3 D4 D5 D6 D7
Figure 2-14. Tx/Rx Timing Diagram of Indicate Mode in STM Interface
Table 2-10. Tx/Rx Timing Values of Indicate Mode in STM Interface Parameter t1 t2 t3 t4 Description S_TX_CLK frequency S_TX(RX)_CLK from S_TX(RX)_DAV DATA Valid after S_TX_CLK S_RX_CLK from Valid DATA output Min 1 1/(4t1) 1/(4t1) 1/(4t1) 1/(4t1) Max 20 1/(4t1) Unit MHz ns ns ns
2-30
S5N8950 DATA SHEET
Envelope Mode in STM Interface
t1 S_TX_CLK t2 S_TX_DAV S_TX_DATA S_RX_CLK t2 S_RX_DAV S_RX_DATA D0 D1 D2 D3 D4 D5 D6 D7 t4 D0 D1 t3
D2
D3
D4
D5
D6
D7
Figure 2-15. Tx/Rx Timing Diagram of Envelope Mode in STM Interface
Table 2-11. Tx/Rx Timing Values of Envelope Mode in STM Interface Parameter t1 t2 t3 t4 Description S_TX_CLK frequency S_TX(RX)_CLK from S_TX(RX)_DAV DATA Valid after S_TX_CLK S_RX_CLK from Valid DATA output Min 1 1/(4t1) 1/(4t1) 1/(4t1) 1/(4t1) Max 20 1/(4t1) Unit MHz ns ns ns
2-31
SAMSUNG ADSL CPE SOLUTION
2-Pin STM Interface
t1 S_TX_CLK t3 t4 S_TX_DATA D0 D1 D2 D3 D4 D5 D6 D7
S_RX_CLK t2 S_RX_DATA D0 D1 D2 D3 D4 D5 D6 D7
Figure 2-16. Tx/Rx Timing Diagram of 2-Pin STM Interface
Table 2-12. Tx/Rx Timing Values of 2-Pin STM Interface Parameter t1 t2 t3 t4 Description S_TX_CLK frequency S_RX_CLK from Valid DATA output DATA Hold after S_TX_CLK DATA Setup before S_TX_CLK Min 1 1/(4t1) 1 1 Max 20 1/(4t1) 3 3 Unit MHz ns ns ns
2-32
S5N8950 DATA SHEET
ELECTRICAL SPECIFICATION
The values presented in the following table apply for all inputs and/or outputs unless specified otherwise. All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device. ABSOLUTE MAXIMUM RATINGS Table 2-13. Absolute Maximum Ratings Symbol ILATCH T STG Latch-up Current Storage Temperature Parameter Rating 200 -65 ~ 150 Unit mA C
RECOMMENDED OPERATING CONDITIONS Table 2-14. Recommended Operating Conditions Symbol VDD DC input Voltage Parameter 1.8 V I/O 3.3V I/O 5V tolerant I/O Analog Core DC Supply Voltage TA Ambient Operating Temperature 1.8V core Rating 1.65 ~ 1.95 3.00 ~ 3.60 3.00 ~ 3.60 1.8 5 % - 40 ~ 85 C Unit V
POWER DISSIPATION Table 2-15. Power Dissipation Symbol PD Parameter Power Dissipation Min Typ < 400 Max Unit mW
2-33
SAMSUNG ADSL CPE SOLUTION
DC CHARACTERISTICS Table 2-16. DC Characteristics Symbol VIH VIL VOH VOL VT VT+ VTIIH IIL IOZ IDD CIN COUT Parameters Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Switching Threshold Schmitt Trigger, Positive-going Threshold Schmitt Trigger, Negative-going Threshold Input High Current (VIN = VDD) Input Low Current (VIN = VSS) Tri-state Output Leakage Current Quiescent Supply Current Input Capacitance Output Capacitance 0.8 -10(10) -10(-60) -10 (33) (-33) 10(60) 10(-10) 10 100 4 4 pF A 1.4 2.0 2.4 0.4 Min 2.0 0.8 Typ Max Unit V
NOTE: ( ) - Input buffer with pull-down
2-34
S5N8950 DATA SHEET
PACKAGE INFORMATION
S5N8950 employs 176 LQPF-2424. Figure shows 176 LQFP-2424 package dimension.
26.00 0.20 0-7 24.00 0.10 0.127 - 0.037
+ 0.0073
0.08 MAX 24.00 0.10 26.00 0.20
176-LQFP-2424
#176 #1 0.50
+ 0.07
0.20 - 0.03 0.08 MAX (1.25) 0.05-0.15 1.40 0.05 1.60 MAX
Figure 2-17. 176 LQFP-2424 Package Dimension
0.45-0.75
2-35
SAMSUNG ADSL CPE SOLUTION
NOTES
2-36
S5N8951 DATA SHEET
OVERVIEW
This chapter provides an overview of the S5N8951X ADSL ATU-C & ATU-R analog front end chip.
GENERAL DESCRIPTIONS
The S5N8951X is Analog Front End IC designed for DMT based universal ADSL (Asymmetric Digital Subscribe Line) modems with 0.35u fully CMOS technology. It has 25.875 ~ 138kHz Upstream channel and 142.312 ~ 1104kHz bandwidth Downstream channel. The S5N8951X includes AGC, LPF, ADC, DAC. The AGC has 40dB gain 0.4dB step in RX mode and -24dB gain 2dB step in TX mode with 12bit/8bit control bits. Anti alias LPF has 1104kHz passband frequency in RX path and 138kHz in TX path. Samsung's ADSL AFE chip provides 14bit ADC at 4.416M or 8.832M sample rates and 14bit 4.416MHz, 8.832MHz DAC. An 10bit DAC support VCXO control for timing recovery. The VCXO is divided into a crystal driver at 35.328MHz.
FEATURES
-- Integrated Analog Front End (AFE) for ADSL ATU-C & ATU-R -- Complies with G.dmt and G.lite -- Up to 1104kHz down stream and 138kHz upstream channel -- 14bit 4.416MHz/s or 8.832MHz/s ADC -- 14bit 4.416MHz or 8.832MHz DAC -- Selectable 14bit or 7bit-2phase ADC/DAC digital interface -- 5 -order Low Pass anti-alias Filter TX/RX paths -- RX 40dB 0.4dB step gain range with 12bit control signal -- TX -24dB 2dB step gain range with 8bit control signal -- 10bit 4kHz VCXO DAC -- Fully 0.35um CMOS technology -- 3.3V Power supply operation -- 0.4W Power comsumption
th
3-1
SAMSUNG ADSL CPE SOLUTION
ABSOLUTE MAXIMUM RATINGS
Table 3-1. Absolute Maximum Ratings Symbol VDD VIN IIN T OPR T STG Parameter DC Supply Voltage DC Input Voltage 5V Tolerant DC Input Current Operation Temperature Storage Temperature Min -0.3 -0.3 -0.3 -10 -40 -40 Typ Max 3.8 VDD+0.3 5.5 10 85 125 Units V V V mA degree C degree C
ELECTRICAL SPECIFICATIONS
Table 3-2. Electrical Specifications Parameter General Power Supply Power Consumption Rx Path THD SNR AGC Gain Minimum Range AGC Gain Maximum Range AGC Step Size AGC Step Error AGC Input Range LPF Cut Off Frequency LPF Output Range LPF Pass Band Ripple LPF Stop Band Attenuation TX Path THD SNR AGC Gain Minimum Range AGC Gain Maximum Range AGC Step Size AGC Step Error 70 70 0 -24 2 0.2 dB dB dB dB 8bit Control 8bit Control -1 60 1104 2 1 70 70 0 40 0.4 0.2 2 dB dB dB dB Vppd kHz Vppd dB dB At 4.416MHz 5th Butterworth 12bit Control 12bit Control 3.0 3.3 450 3.6 V mW Normal Operation Min Typ Max Units Notes/Conditions
3-2
S5N8951 DATA SHEET
Table 3-2. Electrical Specifications (Continued) Parameter AGC Output Range LPF Cut Off Frequency LPF Pass Band Ripple LPF Stop Band Attenuation LPF Input Range ADC Resolution Effective Number Of Bits Sampling Rate Full Scale Input Range DAC Resolution Effective Number Of Bits Sampling Rate Full Scale Output Range VCXO DAC Resolution Sampling Rate Maximum Output Range Minimum Output Range 10 4 2.5 0.5 bits kHz V V 14 12 4.416 2.0 bits bits MHz Vppd Selectable 8.832MHz 14 13 4.416 2.0 bits bits MHz Vppd Selectable 8.832MHz -1 24 2 138 1 Min Typ Max 2 Units Vppd kHz dB dB Vppd At 276kHz 5th Chebyshev Notes/Conditions
3-3
SAMSUNG ADSL CPE SOLUTION
SIGNAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
TX_OUTP TX_DATA[13:0] 14bit DAC TX LPF TX TX_OUTN
MCLK AUXCLK CONT_DAX 10bit DAC CBG SCLK SEN SDIN SDOUT RESETN Auto Tunning Control Logic & Register Band GAP & VIREF
REXT
RX_INP RX_DATA[13:0] RX_INN 14bit ADC RX LPF RX RX_INPG RX_INNG
Figure 3-1. S5N8951X Functional Block Diagram
3-4
S5N8951 DATA SHEET
I/O PINS DESCRIPTION
Table 3-3. I/O Pins Description Signal Name General Pins
RESETN CS0 TM1 TM0 47 48 49 50 CMOS CMOS CMOS CMOS I I I I System Reset. Active Low Chip Select Digital Interface Selection "0" = 14bits, "1" = 7bits*2 "0" = RT, "1" = CO
Num
Type
I/O
Description
DAC Interface
TX_DATA[13:0] MCLK AUXCLK TX_DACOP TX_DACON COMP_DAC IREF_DAC 92~100, 1~5 6 10 88 87 86 85 CMOS CMOS CMOS Analog Analog Analog Analog I I I DAC 14bit Data Inputs If TM1=1, TX_DATA[13:7] is invalid Master Clock 8.832MHz (Selectable 17.664MHz) In 7bits Data Interface mode, AUXCLK=MCLK/2 In 14bits Data Interface mode, pin is open or ground. DAC Current Positive Output for TX path DAC Current Negative Output for TX path Compensation Capacitor 0.1uF Connection for TX path External Resistor 1.24k Connection
ADC Interface
RX_DATA[13:0] RX_ADCIP RX_ADCIN BGR_ADC REFT_ADC REFB_ADC 11~ 24 27 28 31 32 33 CMOS Analog Analog Analog Analog Analog O ADC 14bit Data Outputs (f TM1=1, [13:7] is always low) ADC Positive Input ADC Negative Input ADC Band gap Reference Output ADC Top Reference Output ADC Bottom Reference Output
DSP Interface
SCLK SEN SDOUT SDIN 43 44 45 46 CMOS CMOS CMOS CMOS I I O I Serial Data Clock Serial Data Enable Serial Data Output Serial Data Input
TX Pass Interface
TX_OUTP TX_OUTN TX_FINP TX_FINN 75 74 83 84 Analog Analog Analog Analog Tx Analog Positive Output Tx Analog Positive Output Tx Filter Analog Positive Input Tx Filter Analog Negative Input
3-5
SAMSUNG ADSL CPE SOLUTION
Table 3-3. I/O Pins Description (Continued) Signal Name RX Pass Interface
RX_INP RX_INN RX_INPG RX_INNG RX_FOUTP RX_FOUTN 56 55 54 53 30 29 Analog Analog Analog Analog Analog Analog Rx Analog Positive Input Rx Analog Negative Input Rx Analog External -14dB Gain Positive Input Rx Analog External -14dB Gain Negative Input Rx Filter Analog Positive Output Rx Filter Analog Negative Output
Num
Type
I/O
Description
Voltage Reference
TX_VCOM RX_VCOM REXT_REF 78 62 65 Analog Analog Analog TX Pass Common Mode Voltage Rx Pass Common Mode Voltage Reference Current External Resistor 6.8K
VCXO Interface
CONT_DAX 39 Analog VCXO Control Voltage Output (Only RT)
CO Pass (TM0 = "1")
RX_AOUTP RX_AOUTN RX_FINN RX_FINP TX_AINP TX_AINN TX_FOUTN TX_FOUTP 58 59 60 61 79 80 81 82 Analog Analog Analog Analog Analog Analog Analog Analog Rx AGC Analog Positive Output Rx AGC Analog Negative Output Rx Filter Analog Negative Input Rx Filter Analog Positive Input Tx AGC Analog Positive Input Tx AGC Analog Positive Input Tx Filter Analog Negative Output Tx Filter Analog Negative Output
Power Supply
AVDD_DAC ASUB_DAC AVSS_DAC DVDD_DAC DVSS_DAC AVDD_DAX AVSS_DAX AVDD_ADC ASUB_ADC AVSS_ADC DVDD_ADC 89 90 91 9 7,8 37 38 34 35 36 26 Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Tx Analog DAC VDD Tx Analog DAC SUB Tx Analog DAC VSS Tx Digital DAC VDD Tx Digital DAC VSS VCXO DAC Analog VDD VCXO DAC Analog VSS Rx Analog ADC VDD Rx Analog ADC SUB Rx Analog ADC VSS Rx Digital ADC VDD
3-6
S5N8951 DATA SHEET
Table 3-3. I/O Pins Description (Continued) Signal Name
DVSS_ADC AVDD_TX AVSS_TX ASUB_TX AVDD_FAT AVSS_FAT AVDD_RX AVSS_RX ASUB_RX AVDD_REF AVSS_REF ASUB_REF DVDD_CTL DSUB_CTL DVSS_CTL
Num
25 76,77 72,73 71 69,70 67.68 57 52 51 66 64 63 40 41 42
Type
Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply
I/O
Rx Digital ADC VSS Tx Path VDD Tx Path VSS TX Path SUB Filter Auto Tuning VDD Filter Auto Tuning VSS Rx Filter VDD Rx Filter VSS Rx Filter SUB Reference VDD Reference VSS Reference SUB Control Logic VDD Digital Substrate VSS Control Logic VSS
Description
3-7
SAMSUNG ADSL CPE SOLUTION
PIN CONFIGURATIONS (TOP VIEW)
TX_DATA4 TX_DATA3 TX_DATA2 TX_DATA1 TX_DATA0 MCLK DVSS_DAC DVSS_DAC DVDD_DAC AUX_CLK RX_DATA0 RX_DATA1 RX_DATA2 RX_DATA3 RX_DATA4 RX_DATA5 RX_DATA6 RX_DATA7 RX_DATA8 RX_DATA9 RX_DATA10 RX_DAT11 RX_DATA12 RX_DATA13 DVSS_ADC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
TX_DATA5 TX_DATA6 TX_DATA7 TX_DATA8 TX_DATA9 TX_DATA10 TX_DATA11 TX_DATA12 TX_DATA13 AVSS_DAC ASUB_DAC AVDD_DAC TX_DACOP TX_DACON COMP_DAC IREF_DAC TX_FINN TX_FINP TX_FOUTP TX_FOUTN TX_AINN TX_AINP TX_ACCOM AVDD_TX AVDD_TX
S5N8951X
100-TQFP
(Top View)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TX_OUTP TX_OUTN AVSS_TX AVSS_TX ASUB_TX AVDD_FAT AVDD_FAT AVSS_FAT AVSS_FAT AVDD_REF REXT_REF AVSS_REF ASUB_REF RX_VCOM RX_FINP RX_FINN RX_AOUTN RX_AOUTP AVDD_RX RX_INP RX_INN RX_INPG RX_INNG AVSS_RX ASUB_RX
3-8
DVDD_ADC RX_ADCIP RX_ADCIN RX_FOUTN RX_FOUTP BGR_ADC REFT_ADC REFB_ADC AVDD_ADC ASUB_ADC AVSS_ADC AVDD_DAX AVSS_DAX CONT_DAX DVDD_CTL DSUB_CTL DVSS_CTL SCLK SEN SDOUT SDIN RESETN CS0 TM1 TM0
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Figure 3-2. Pin Configurations (Top View)
S5N8951 DATA SHEET
BLOCK DESCRIPTIONS ADC / DAC
S5N8951X has a 14bit resolution ADC 4.416M/8.832M sample frequency. The input of ADC is fully differential 2.0Vppd Max. The ADC transforms the signal into a digital 14bit output. There are two type of DAC's in S5N8951X. One is for TX. It is 14bit 4.416MHz/8.832MHz frequency. Samsung's DMT (S5N8950) transmit 14bit parallel data to the AFE chip. The other DAC is for VCXO control. It has 10bit resolution 4kHz frequency. Internal registers of S5N8951X transform 10bit VCXO control serial data from DSP into 10bit parallel data. And VCXO output analog signal CONT_DAX (Pin #39).
TX/RX LPF
RX FILTERS The combination of the external filter (an LC ladder filter typically) with the integrated low pass filter must provide: -- DMT sidelobe and out of band (anti-aliasing) attenuation -- Anti alias filter (60dB rejection @ image frequency) -- On chip tuning circuit included.
TX FILTERS The TX Filters act not only to suppress the DMT sidebands but also as smoothing filters on the D/A converter's output to suppress the image spectrum. For this reason they are realized in a time continuous approach and on chip tuning circuit included
3-9
SAMSUNG ADSL CPE SOLUTION
TX/RX AGC
TX AGC has 0 ~ -24dB gains with 2dB step. It is controlled through 8bit serial digital signal from DSP. Internal registers of Samsung AFE Chips transform 8bit parallel control data. It outputs 2Vppd fully differential signal to line driver. RX AGC has low noise 0~40dB gains with 0.4dB step and It is controlled through 12bit + 1MSB control signal. If 1MSB is high, another RX input pass pin#53 RX_INNG #54 RX_INNP (For example, external -14dB gain pass) is seclected. It inputs 2Vppd fully differential signal to RX LPF.
3-10
S5N8951 DATA SHEET
DIGITAL SIGNAL INTERFACE COMMAND SIGNAL INTERFACE
This description hold for ATU-R (S5N8951X). The chip consists of four kinds of register map: -- Power Control -- Transmitter AGC -- Receiver AGC -- VCXO Control -- Clock Selection Serial interfaces use three pins: -- Clock -- Serial data input (25-bit: 2bit cs + 5bit address + 1bit r/w + 16 bit data + 1bit dummy) -- Serial data output (16 bit data) -- Enable
3-11
SAMSUNG ADSL CPE SOLUTION
SERIAL DATA CONFIGURATION Table 3-4. Serial Data Configuration Register CS Address R/ W Serial Data (SDAT) Data D u m m y D 6 P C 6 T A 6 R A 6 V C 6 X D 5 P C 5 T A 5 R A 5 V C 5 X D 4 P C 4 T A 4 R A 4 V C 4 X D 3 P C 3 T A 3 R A 3 V C 3 X D 2 P C 2 T A 2 R A 2 V C 2 X D 1 P C 1 T A 1 R A 1 V C 1 C K 1 D 0 P C 0 T A 0 R A 0 V C 0 C K 0 X
C S 1 PWR_CTL C S 0 C S 0 C S 0 C S 0 C S 0
C S 0 C S 0 C S 0 C S 0 C S 0 C S 0
A 4 X
A 3 X
A 2 0
A 1 0
A R/ D D D D D D D 0 W 15 14 13 12 11 10 9 0 R/ X W 1 R/ X W 0 R/ X W 1 R/ X W 0 R/ X W X X X X X X
D 8 X
D 7 P C 7 T A 7 R A 7 V C 7 X
X
TX_AGC
X
X
0
0
X
X
X
X
X
X
X
X
RX_AGC
X
X
0
1
X
X
RRRR AAAA 12 11 10 9 X X X V C 9 X
R A 8 V C 8 X
X
VCXO_CTL
X
X
0
1
X
X
X
CLK_SEL
X
X
1
0
X
X
X
X
X
X
NOTE: X = Don't care R/W =0 Read R/W =1 Write
3-12
S5N8951 DATA SHEET
REGISTER MAP Power Control The power on/off control of AFE blocks on this chip is set by the PWR_CTL register, (XX000), as described below: Table 3-5. PWR_CTL Register (A4A3A2A1A0=XX000) Data Name Reset Value D15 D14 D13 D12 D11 D10 D9 D8 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Power Control is as follow. Table 3-6. Power Control Register Value PC7 0 0 0 0 0 0 0 0 1 0 0 0 1 PC6 0 0 0 0 0 0 0 1 0 0 0 1 1 PC5 0 0 0 0 0 0 1 0 0 0 0 1 1 PC4 0 0 0 0 0 1 0 0 0 0 0 1 1 PC3 0 0 0 0 1 0 0 0 0 0 1 0 1 PC2 0 0 0 1 0 0 0 0 0 0 1 0 1 PC1 0 0 1 0 0 0 0 0 0 1 0 0 1 PC0 0 1 0 0 0 0 0 0 0 1 0 0 1 HEX 0000 0001 0002 0004 0008 0010 0020 0040 0080 0003 000C 0070 00FF N/A N/A TX DAC Power Down TX Filter & AGC Power Down RX ADC Power Down Rx Filter Power Down Rx AGC Power Down VCXO DAC Power Down N/A TX Path Power Down Rx Path Power Down Whole Chip Power Down Descripcion Normal Operation
Adding Power Down (based on upper power down)
3-13
SAMSUNG ADSL CPE SOLUTION
Transmitter AGC The main functions of the TX path are controlled by the TX_AGC registers, as described below: Table 3-7. TX_AGC Register (A4A3A2A1A0=XX001) Data Name Reset Value D15 D14 D13 D12 D11 D10 D9 D8 D7 TA7 0 D6 TA6 0 D5 TA5 0 D4 TA4 1 D3 TA3 0 D2 TA2 0 D1 TA1 0 D0 TA0 1
TA[7:0] TX path output attenuator gain setting. 0 to -24dB attenuation in 2dB steps. (default is 0dB). Table 3-8. Transmitter AGC Register Value TA[7] 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 TA[6] 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 TA[5] 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 TA[4] 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 TA[3] 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 TA[2] 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 TA[1] 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 TA[0] 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 HEX 0011 0012 0014 0018 0021 0022 0024 0028 0041 0042 0044 0048 0081 0082 0084 0088 GAIN (dB) 0 -2 -4 -6 -6 -8 -10 -12 -12 -14 -16 -18 -18 -20 -22 -24
3-14
S5N8951 DATA SHEET
Recieve AGC The main functions of the RX path are controlled by the RX_AGC register, as described below: Table 3-9. RX_AGC Register (A4A3A2A1A0=XX010) Data Name Reset Value D15 D14 D13 D12 RA 12 0 D11 RA 11 0 D10 RA 10 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RA9 RA8 RA7 RA6 RA4 RA4 RA3 RA2 RA1 RA0 0 0 1 0 0 1 0 0 0 0
3-15
SAMSUNG ADSL CPE SOLUTION
RA[11:0]: Receive path input gain setting 0 to 40dB gain in 0.4dB steps. (default is 0dB). RA[12] is "1",the external attenuation gain(For example -14dB) path pin#53 RX_INNG #54 RX_INPG will be enable. RA[12] should only be utilized the short line conditions. Table 3-10. RX Gain Register Value RA [12] 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RA [11] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 RA [10] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 RA [9] 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 RA [8] 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 RA [7] 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 RA [6] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 RA [5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 RA [4] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RA [3] RA [2] RA [1] RA [0] HEX 1090 ~ 109F 1110 ~ 111F 1210 ~ 121F 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 009A 009B 009C 009D 009E 009F 0110 ~ 011F 0210 ~ 021F 0410 ~ 041F 0810 ~ 081F 0820 ~ 082F 0840 ~ 084F GAIN(dB) -14.0 ~ -8.0 -8.0 ~ -2.0 -2.0 ~ 4.0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 6.0 ~ 12.0 12.0 ~ 18.0 18.0 ~ 24.0 24.0 ~ 30.0 30.0 ~ 36.0 36.0 ~ 40.0
0000 ~ 1111 0000 ~ 1111 0000 ~ 1111 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0000 ~ 1111 0000 ~ 1111 0000 ~ 1111 0000 ~ 1111 0000 ~ 1111 0000 ~ 1111
3-16
S5N8951 DATA SHEET
VCXO Control The VCXO DAC is 10-bit voltage-mode DAC designed to be monotonic and intended to be operated at a 4kHz update rate. In order to update the DAC, the user must write to the VCXO register through the serial port. The individual bit definitions are given below. Table 3-11. VCXO_CTL Register (A4A3A2A1A0=XX011) Data Name Reset Value D15 D14 D13 D12 D11 D10 D9 1 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
VC9 VC8 VC7 VC6 VC4 VC4 VC3 VC2 VC1 VC0
VC[9:0]: VCXO DAC 10-bit word. The DAC nominal output voltages for extreme and mid-scale codes are as follows. -- VC[9:0] = 0000000000 = 0.5V -- VC[9:0] = 1000000000 = 1.5V (mid-range) -- VC[9:0] = 1111111111 = 2.5V A general expression for the DAC output voltage is 0.5V + (CODE / 1024) X (2.0V) where CODE is the decimal integer value of the 10-bit word formed by VCXO[9:0].
3-17
SAMSUNG ADSL CPE SOLUTION
Clock Selection Main functions of Clock Selection are frequency selection of each MCLK/AUXCLK/ADC. The individual bit definitions are given below. Table 3-12. CLK_SEL Register (A4A3A2A1A0=XX100) Data Name Reset Value D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 0 D0 0
CK1 CK0
TM1, CK[1:0]: Clock Selection has eight possible clocking configuration as follow. Table 3-13. Clock Configuration TM1 0 0 0 0 1 1 1 1 2 Phase OFF OFF OFF OFF ON ON ON ON CK1 0 0 1 1 0 0 1 1 CK0 0 1 0 1 0 1 0 1 HEX 0000 0001 0002 0003 0000 0001 0002 0003 MCLK 4.416MHz 4.416MHz 8.832MHz 8.832MHz 8.832MHz 8.832MHz 17.664MHz 17.664MHz AUXCLK 0 0 0 0 4.416MHz 4.416MHz 8.832MHz 8.832MHz DAC 4.416MHz 4.416MHz 8.832MHz 8.832MHz 4.416MHz 4.416MHz 8.832MHz 8.832MHz ADC 2.208MHz 4.416MHz 4.416MHz 8.832MHz 4.416MHz 2.204MHz 8.832MHz 4.416MHz
3-18
S5N8951 DATA SHEET
SERIAL DATA INTERFACE Physical Interface Serial interfaces use three pins: -- Clock -- Serial data (25-bit: 2bit cs + 5bit address + 1bit r/w + 16 bit data + 1bit dummy) -- Enable
AFE_SCLK S5N8950 (DMT) AFE_SEN AFE_SDOUT AFE_SDIN S5N8951X (AFE)
Figure 3-3. Control Register Interface
Waveform
TSU1 SEN
TCYC TPWL TPWH TH2
TSU TH1
TPW
SCLK
SDIN
CS1 CS0
A4
A3
A2
A1
A0
R/W D15 TD3
D14
----
D1
D0
Dummy TD4
SDOUT
D15
D14
----
D1
D0
Figure 3-4. Register Control Waveform
3-19
SAMSUNG ADSL CPE SOLUTION
Table 3-14. Register Control Timing Symbol Parameter SCLK Clock Period SCLK High Time SCLK Low Time SEN Low To SCLK High SCLK High to SEN High SEN Inactive Pulse Time SDIN Setup Time SDIN Hold Time SCLK Low To SDOUT Delay SEN Inactive To SDOUT HiZ TCYC T PWH T PWL TSU1 T H1 TPW TSU2 T H2 T D3 T D4 452 452 30 15 905 15 15 30 30 905 nS nS nS nS nS nS nS nS nS nS Min Typ Max Unit Note
DATA INTERFACE
PHYSICAL INTERFACE -- ADC and DAC data transmission between S5N8951X and S5N8950 -- Parallel Interface: 29 pin (14 ADC bit data, 14 DAC bit data, MCLK)
-- Parallel Interface (2phase): 16 pin (7 ADC bit data, 7 DAC bit data, MCLK, AUXCLK)
TX_DATA[13:0] S5N8950 (DMT) RX_DATA[13:0] MCLK S5N8951X (AFE)
Figure 3-5. Data Interface
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S5N8951 DATA SHEET
Waveform
TD MCLK
TPWH
TCYC TPWL
TD
TX_DATA
TX_DATA[13:0]
TX_DATA[13:0]
TX_DATA[13:0] TSU
TX_DATA[13:0] TH
RX_DATA
RX_DATA[13:0]
RX_DATA[13:0]
Figure 3-6. Data Interface Timing
Table 3-15. Data Interface Timing Parameter MCLK Clock Period MCLK High Time MCLK Low Time DATA Delay after MCLK RX_DATA setup to MCLK RX_DATA hold to MCLK AUXCLK setup to MCLK AUXCLK hold to MCLK Symbol T CYC TPWH TPWL TD TSU TH T SU2 TH2 15 42 10 10 Min Typ 113 57 57 10 Max Unit nS nS nS nS nS nS nS nS MCLK=4.416MHz MCLK=4.416MHz Note MCLK=4.416MHz MCLK=4.416MHz MCLK=4.416MHz
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SAMSUNG ADSL CPE SOLUTION
APPLICATION CIRCUIT
37.5 37.5 1.24k 1u 0.1u AVDD_TX 0.1u 0.1u 1k 1k
AVSS_TX DA<13:0> DVDD_AFE TX_DATA5 100 TX_DATA6 99 TX_DATA7 98 TX_DATA8 97 TX_DATA9 96 TX_DATA10 95 TX_DATA11 94 TX_DATA12 93 TX_DATA13 92 AVSS_DAC91 ASUB_DAC90 AVDD_DAC89 TX_DACOP88 TX_DACON87 COMP_DAC86 IREF_DAC85 TX_FINN84 TX_FINP83 TX_FOUTP82 TX_FOUTN81 TX_AINN80 TX_AINP79 TX_VCOM78 AVDD_TX77 AVDD_TX76
39n 39n TX_OUTP TX_OUTN 5.1k 5.1k
MCLK
6.8k
S5N8951X
(100 - TQFP)
S5N8950 Interface
AD<13:0>
39n RX_INP 4.7k 330 1u 330 4.7k RX_INN 39n
DVSS_AFE
26DVDD_ADC 27RX_ADCIP 28RX_ADCIN 29RX_FOUTN 30RX_FOUTP 31BGR_ADC 32REFT_ADC 33REFB_ADC 34AVDD_ADC 35ASUB_ADC 36AVSS_ADC 37AVDD_DAX 38AVSS_DAX 39CONT_DAX 40DVDD_CTL 41DSUB_CTL 42DVSS_CTL 43SCLK 44SEN 45SDOUT 46SDIN 47RESETN 48CS0 49TM1 50TM0
AVDD_RX AVDD_ADC
0.1u 0.1u
AVSS_ADC
AVSS_RX
VDD_AFE
AVDD_TX
AVDD_RX
AVDD_ADC
10u SCLK SEN SDOUT SDIN
0.1u
10u
0.1u
10u
0.1u
0.5u 10u
0.5u 1u AVSS_RX
0.5u 0.1u AVSS_ADC
AVSS_ADC AVSS_TX DVDD_AFE RESETN CS0 0.5u 0.1u VSS_AFE System Interface 1u DVSS_AFE 0.5u
Figure 3-7. ATU-R Application Circuit
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VCXO
Line Interface
AUXCLK
1TX_DATA4 2TX_DATA3 3TX_DATA2 4TX_DATA1 5TX_DATA0 6MCLK 7DVSS_DAC 8DVSS_DAC 9DVDD_DAC 10AUX_CLK 11RX_DATA0 12RX_DATA1 13RX_DATA2 14RX_DATA3 15RX_DATA4 16RX_DATA5 17RX_DATA6 18RX_DATA7 19RX_DATA8 20RX_DATA9 21RX_DATA10 22RX_DATA11 23RX_DATA12 24RX_DATA13 25DVSS_ADC
TX_OUTP75 TX_OUTN74 AVSS_TX73 AVSS_TX72 ASUB_TX71 AVDD_FAT70 AVDD_FAT69 AVSS_FAT68 AVSS_FAT67 AVDD_REF66 REXT_REF65 AVSS_REF 64 ASUB_REF63 RX_VCOM62 RX_FINP61 RX_FINN60 RX_AOUTN59 RX_AOUTP58 AVDD_RX57 RX_INP56 RX_INN55 RX_INPG54 RX_INNG53 AVSS_RX52 ASUB_RX51
S5N8951 DATA SHEET
PACKAGE INFORMATION (100-TQFP-1414)
16.00 0.20 14.00 0-7 0.127
+ 0.073 - 0.037
16.00 0.20
14.00
100-TQFP-1414
0.08 MAX
#100
#1 0.50
+ 0.07
0.20 - 0.03 0 .0 8 M A X 0.05-0.15 (1.00) 1.00 0.05 1.20 MAX
Figure 3-8. Package Dimension
0.45-0.75
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SAMSUNG ADSL CPE SOLUTION
Table 3-16. Revision History Revision No. 1.0 2.0 Date 2000-07-20 2001-03-27 S5N8951X (Rev.1) Released. Pin Type changed (100-QFP-1420C 100-TQFP-1414) Description
IMPORTANT NOTICE The information furnished by Samsung Electronics in this document is belived to be accurate and reliable. However, no resposibility is assumed by Samsung Electronics for its use, nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Samsung Electronics. Samsung Electronics reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. Copyright (c)2002 Samsung Electronics, Inc. All Rights Reserved
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